[N8VEM: 16450] The new 6x0x-6U board comments

[Borut]

Hi all!

Since previous topic contains almost 100 posts, i propose a new topic for
discussion of 6x0x-6U design.
John Coffman put the schematics on the N8VEM site.
http://n8vem-sbc.pbworks.com/w/file/70468199/6x0x-6U.pdf

I think there is a missing gnd pin on P29, 4 pin connector for serial ttl
signals in i/o part.
i would also like a RTC (DS1302), maybe connected to one of 6522 VIAs.
Both FLEX2 and FLEX9 require user to type in current date during startup. I
don't know about OS9.

Did 6821 PIA get lost in transfer or is there any other means of
communicating with propeller?

We will put the whole I/O into different memory segment (E8xxh-EFFFh), so
lets discard the addressing logic consisting of
U31, U35, U39, U22bcd and use partial decode - one negative chip select on
/CS0 and a positive address line on CS1.
For example:
negative chip select /IOSEL-E9xx and
A4 selects ACIA @ E910h
A5 selects PTM @ E920h
A6 selects VIA0 @ E940h
A7 selects VIA1 @ E980h


I would rather than full support for 6802 have minimal support for it,
which means no internal ram, no backup for internal ram etc.
Internal ram makes sense when the board would be used in an embedded
environment, but the purpose of this board (as i understand from discussion)
is more to support 'vintage' operating systems. In 6802's case that would
be FLEX2, which can not use nonvolatile ram at location 00 - 7Fh anyway.

Instead i would prefer additional support for 65816 with a latch for higher
address lines (a16-a23), which could be jumpered to
outputs from U9 in MMU part (mA16 - mA19).

Best regards,
Borut

[Andrew Lynch]

Hi! Thanks Borut! The schematic is obsolete as the design is going through
a major revision.



Basically we are starting over with a new modular schematic with an MMU,
improved CPU sockets, RTC and many other changes.



Hopefully in a few days we can post an updated schematic and then we can
review it then.



Thanks and have a nice day!

Andrew Lynch



From: n8vem-/***@public.gmane.org [mailto:n8vem-/***@public.gmane.org] On Behalf Of
Borut
Sent: Saturday, November 02, 2013 4:46 PM
To: n8vem-/***@public.gmane.org
Subject: [N8VEM: 16450] The new 6x0x-6U board comments



Hi all!

Since previous topic contains almost 100 posts, i propose a new topic for
discussion of 6x0x-6U design.
John Coffman put the schematics on the N8VEM site.
http://n8vem-sbc.pbworks.com/w/file/70468199/6x0x-6U.pdf

I think there is a missing gnd pin on P29, 4 pin connector for serial ttl
signals in i/o part.
i would also like a RTC (DS1302), maybe connected to one of 6522 VIAs.
Both FLEX2 and FLEX9 require user to type in current date during startup. I
don't know about OS9.

Did 6821 PIA get lost in transfer or is there any other means of
communicating with propeller?

We will put the whole I/O into different memory segment (E8xxh-EFFFh), so
lets discard the addressing logic consisting of
U31, U35, U39, U22bcd and use partial decode - one negative chip select on
/CS0 and a positive address line on CS1.
For example:
negative chip select /IOSEL-E9xx and
A4 selects ACIA @ E910h
A5 selects PTM @ E920h
A6 selects VIA0 @ E940h
A7 selects VIA1 @ E980h


I would rather than full support for 6802 have minimal support for it, which
means no internal ram, no backup for internal ram etc.
Internal ram makes sense when the board would be used in an embedded
environment, but the purpose of this board (as i understand from discussion)
is more to support 'vintage' operating systems. In 6802's case that would be
FLEX2, which can not use nonvolatile ram at location 00 - 7Fh anyway.

Instead i would prefer additional support for 65816 with a latch for higher
address lines (a16-a23), which could be jumpered to
outputs from U9 in MMU part (mA16 - mA19).

Best regards,
Borut
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[Ian May]

Borut decoding the I/O like that is ok for FLEX but horribly wasteful for
OS9. The MC6883 (74LS783) SAM chip in the COCO 2 fits all the I/O into the
top page of memory, so a COCO with 64K of ram only loses 256 bytes for all
the I/O and interrupt vectors. Decoding lots of 1's is easy with a 74LS133
13 input NAND gate. If you give it the top 8 address lines and an inverted
A7 you produce an active low signal from FF00-FF7F and you still have 4
inputs left (one of which could be allocated to the 6802's VMA).

Cheers,
Ian.

Post by Borut
Hi all!
Since previous topic contains almost 100 posts, i propose a new topic for
discussion of 6x0x-6U design.
John Coffman put the schematics on the N8VEM site.
http://n8vem-sbc.pbworks.com/w/file/70468199/6x0x-6U.pdf
I think there is a missing gnd pin on P29, 4 pin connector for serial ttl
signals in i/o part.
i would also like a RTC (DS1302), maybe connected to one of 6522 VIAs.
Both FLEX2 and FLEX9 require user to type in current date during startup.
I don't know about OS9.
Did 6821 PIA get lost in transfer or is there any other means of
communicating with propeller?
We will put the whole I/O into different memory segment (E8xxh-EFFFh), so
lets discard the addressing logic consisting of
U31, U35, U39, U22bcd and use partial decode - one negative chip select on
/CS0 and a positive address line on CS1.
negative chip select /IOSEL-E9xx and
I would rather than full support for 6802 have minimal support for it,
which means no internal ram, no backup for internal ram etc.
Internal ram makes sense when the board would be used in an embedded
environment, but the purpose of this board (as i understand from discussion)
is more to support 'vintage' operating systems. In 6802's case that would
be FLEX2, which can not use nonvolatile ram at location 00 - 7Fh anyway.
Instead i would prefer additional support for 65816 with a latch for
higher address lines (a16-a23), which could be jumpered to
outputs from U9 in MMU part (mA16 - mA19).
Best regards,
Borut
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