Discussion:
[N8VEM: 16171] SBCv2 debugging
opticpow
2013-09-23 10:02:21 UTC
Permalink
Hi All,

It has been a bit of a while (well long while actually) but life and all
that!

Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
debugging again. Current status is that scream works (lots of zeros). Next
test I've tried is this code (I believe John C suggested this):

start:
ld a,0ffh ; -> Put all ones in the accumulator
ld (8000h),a ; -> Store the contents of the accumulator at the
specified location
ld a,(8000h) ; -> Load the contents of the specified memory
location in the accumulator
cp 0ffh ; -> Compare actual with expected
jp z,start ; -> Jump back to beginning if actual = expected
halt ; -> actual did not match expected so halt
end


Running this give me a Red Halt on the led, so I guess there is an issue
with the RAM. I've been studying the schematic, but I'm not quite sure
which of the chips would be required for this process. I'm guessing not the
extended addressing logic so maybe:

U23 (obviously)
U21
and U4 U14 U6 from the IO decode logic??

Thanks,

Wayne.

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p***@public.gmane.org
2013-09-23 10:10:44 UTC
Permalink
Wayne,

Can you test the same store/load sequence manually with the ROM monitor (both at the same address and other addresses)?
Also, can you put 1 or more NOPs in your program to delay a little bit the store/load memory accesses, and tell us whether this made any change in the halting behavior?

Regards,
picmaster

-------------------------------------

Наети сървъри в Германия от 82лв/м с ДДС
AMD AthlonTM X2, 4 GB RAM DDR2, 2x320 GB SATA II-HDD
http://www.icn.bg/bg/news/news26.html
http://www.icn.bg/bg/news/news26.html

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opticpow
2013-09-23 10:19:37 UTC
Permalink
Hi Picmaster, I'll try with the NOPs. Where would I locate the rom monitor??

Wayne.

On Monday, September 23, 2013 8:10:44 PM UTC+10, picmaster wrote:
>
> Wayne,
>
> Can you test the same store/load sequence manually with the ROM monitor
> (both at the same address and other addresses)?
> Also, can you put 1 or more NOPs in your program to delay a little bit the
> store/load memory accesses, and tell us whether this made any change in the
> halting behavior?
>
> Regards,
> picmaster
>
> -------------------------------------
>
> Íàåòè ñúðâúðè â Ãåðìàíèÿ îò 82ëâ/ì ñ ÄÄÑ
> AMD AthlonTM X2, 4 GB RAM DDR2, 2x320 GB SATA II-HDD
> http://www.icn.bg/bg/news/news26.html
> http://www.icn.bg/bg/news/news26.html
>
>

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p***@public.gmane.org
2013-09-23 10:54:00 UTC
Permalink
Hi Wayne,

When you boot you system, you should see the ROM prompt (this is from N8VEM_std.rom):


RomWBW...

N8VEM Z80 @ 8MHz ROM=512KB RAM=512KB
UART0: IO=0x68 <NOT PRESENT>
MD: UNITS=2 ROMDISK=448KB RAMDISK=416KB

N8VEM HBIOS v2.5.1, Build 17, 25-Jun-2013

A=RAM B=ROM
Boot: (M)onitor, (R)OM, or Drive Letter ===> M


Select "M" and you'll now see the Monitor prompt, where you can edit/examine your board's memory.

Regards,
picmaster

-------------------------------------

Наети сървъри в Германия от 82лв/м с ДДС
AMD AthlonTM X2, 4 GB RAM DDR2, 2x320 GB SATA II-HDD
http://www.icn.bg/bg/news/news26.html
http://www.icn.bg/bg/news/news26.html

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Max Scane
2013-09-23 10:44:54 UTC
Permalink
Hi Wayne,

8000h is the first accessible ram address. Upon power on the ROM is
switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
8000-FFFF. The test result looks like you can't access/write to the RAM.

I would check the following:

1. Check RAM jumper
2. Check MCPL jumpers (set to default)
3. Replace RAM chip
4. Modify program to continuously loop reading/writing to RAM
5. Check with CRO or Logic probe for activity on the CS and /WR pins on the
RAM

Jumper settings can be found at:
http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings

I hope this helps.

Regards,

Max



On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wayne-***@public.gmane.org> wrote:

> Hi All,
>
> It has been a bit of a while (well long while actually) but life and all
> that!
>
> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
> debugging again. Current status is that scream works (lots of zeros). Next
> test I've tried is this code (I believe John C suggested this):
>
> start:
> ld a,0ffh ; -> Put all ones in the accumulator
> ld (8000h),a ; -> Store the contents of the accumulator at the
> specified location
> ld a,(8000h) ; -> Load the contents of the specified memory
> location in the accumulator
> cp 0ffh ; -> Compare actual with expected
> jp z,start ; -> Jump back to beginning if actual = expected
> halt ; -> actual did not match expected so halt
> end
>
>
> Running this give me a Red Halt on the led, so I guess there is an issue
> with the RAM. I've been studying the schematic, but I'm not quite sure
> which of the chips would be required for this process. I'm guessing not the
> extended addressing logic so maybe:
>
> U23 (obviously)
> U21
> and U4 U14 U6 from the IO decode logic??
>
> Thanks,
>
> Wayne.
>
> --
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opticpow
2013-09-24 13:18:12 UTC
Permalink
Hi Max,

Attached is a high res of my board.

1. All jumpers are in the default positions, except for K6 & K8, as I'm
using Flash ROM (29F040)
2. As above. Did double check
3. I have two RAM chips, both identical (you can see one clearly in the
pic) both give the same result. I'd doubt both would be faulty / damaged?
4. Done:

start:
ld a,0ffh ; -> Put all ones in the accumulator
ld (8000h),a ; -> Store the contents of the accumulator at the
specified location
nop
nop
ld a,(8000h) ; -> Load the contents of the specified memory
location in the accumulator
nop
nop
jp start ; -> Jump back to beginning if actual = expected
end

5. /WR is wiggling between 4.1 & 4.5MHz with the above code. I could not
see a CS on the schematic for the RAM chip, I did see /CS on pin 5 of the
DS1302. Is this what you mean? I see no activity on pin 5 with above
program running.

Thanks for you help.

Wayne.


On Monday, September 23, 2013 8:44:54 PM UTC+10, Max Scane wrote:
>
> Hi Wayne,
>
> 8000h is the first accessible ram address. Upon power on the ROM is
> switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
> 8000-FFFF. The test result looks like you can't access/write to the RAM.
>
> I would check the following:
>
> 1. Check RAM jumper
> 2. Check MCPL jumpers (set to default)
> 3. Replace RAM chip
> 4. Modify program to continuously loop reading/writing to RAM
> 5. Check with CRO or Logic probe for activity on the CS and /WR pins on
> the RAM
>
> Jumper settings can be found at:
>
> http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings
>
> I hope this helps.
>
> Regards,
>
> Max
>
>
>
> On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wa...-***@public.gmane.org<javascript:>
> > wrote:
>
>> Hi All,
>>
>> It has been a bit of a while (well long while actually) but life and all
>> that!
>>
>> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
>> debugging again. Current status is that scream works (lots of zeros). Next
>> test I've tried is this code (I believe John C suggested this):
>>
>> start:
>> ld a,0ffh ; -> Put all ones in the accumulator
>> ld (8000h),a ; -> Store the contents of the accumulator at the
>> specified location
>> ld a,(8000h) ; -> Load the contents of the specified memory
>> location in the accumulator
>> cp 0ffh ; -> Compare actual with expected
>> jp z,start ; -> Jump back to beginning if actual = expected
>> halt ; -> actual did not match expected so halt
>> end
>>
>>
>> Running this give me a Red Halt on the led, so I guess there is an issue
>> with the RAM. I've been studying the schematic, but I'm not quite sure
>> which of the chips would be required for this process. I'm guessing not the
>> extended addressing logic so maybe:
>>
>> U23 (obviously)
>> U21
>> and U4 U14 U6 from the IO decode logic??
>>
>> Thanks,
>>
>> Wayne.
>>
>> --
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>> "N8VEM" group.
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>> email to n8vem+un...-/***@public.gmane.org <javascript:>.
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>>
>
>

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Ants Pants
2013-09-24 15:57:07 UTC
Permalink
HI Wayne,

could you please tell us what is the frequency of you CPU clock oscillator
can?

Regards,
Tony


On Wed, Sep 25, 2013 at 1:18 AM, opticpow <wayne-***@public.gmane.org> wrote:

> Hi Max,
>
> Attached is a high res of my board.
>
> 1. All jumpers are in the default positions, except for K6 & K8, as I'm
> using Flash ROM (29F040)
> 2. As above. Did double check
> 3. I have two RAM chips, both identical (you can see one clearly in the
> pic) both give the same result. I'd doubt both would be faulty / damaged?
> 4. Done:
>
> start:
> ld a,0ffh ; -> Put all ones in the accumulator
> ld (8000h),a ; -> Store the contents of the accumulator at the
> specified location
> nop
> nop
>
> ld a,(8000h) ; -> Load the contents of the specified memory
> location in the accumulator
> nop
> nop
> jp start ; -> Jump back to beginning if actual = expected
> end
>
> 5. /WR is wiggling between 4.1 & 4.5MHz with the above code. I could not
> see a CS on the schematic for the RAM chip, I did see /CS on pin 5 of the
> DS1302. Is this what you mean? I see no activity on pin 5 with above
> program running.
>
> Thanks for you help.
>
> Wayne.
>
>
>
> On Monday, September 23, 2013 8:44:54 PM UTC+10, Max Scane wrote:
>
>> Hi Wayne,
>>
>> 8000h is the first accessible ram address. Upon power on the ROM is
>> switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
>> 8000-FFFF. The test result looks like you can't access/write to the RAM.
>>
>> I would check the following:
>>
>> 1. Check RAM jumper
>> 2. Check MCPL jumpers (set to default)
>> 3. Replace RAM chip
>> 4. Modify program to continuously loop reading/writing to RAM
>> 5. Check with CRO or Logic probe for activity on the CS and /WR pins on
>> the RAM
>>
>> Jumper settings can be found at:
>> http://n8vem-sbc.pbworks.com/**w/page/39172478/N8VEM%20SBC%**
>> 20V2%20Jumper%20Settings<http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings>
>>
>> I hope this helps.
>>
>> Regards,
>>
>> Max
>>
>>
>>
>> On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wa...-***@public.gmane.org> wrote:
>>
>>> Hi All,
>>>
>>> It has been a bit of a while (well long while actually) but life and all
>>> that!
>>>
>>> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
>>> debugging again. Current status is that scream works (lots of zeros). Next
>>> test I've tried is this code (I believe John C suggested this):
>>>
>>> start:
>>> ld a,0ffh ; -> Put all ones in the accumulator
>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>> the specified location
>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>> location in the accumulator
>>> cp 0ffh ; -> Compare actual with expected
>>> jp z,start ; -> Jump back to beginning if actual = expected
>>> halt ; -> actual did not match expected so halt
>>> end
>>>
>>>
>>> Running this give me a Red Halt on the led, so I guess there is an issue
>>> with the RAM. I've been studying the schematic, but I'm not quite sure
>>> which of the chips would be required for this process. I'm guessing not the
>>> extended addressing logic so maybe:
>>>
>>> U23 (obviously)
>>> U21
>>> and U4 U14 U6 from the IO decode logic??
>>>
>>> Thanks,
>>>
>>> Wayne.
>>>
>>> --
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>>> Groups "N8VEM" group.
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>>> .
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>>> .
>>>
>>
>> --
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opticpow
2013-09-25 00:14:29 UTC
Permalink
Hi Tony, I currently have a 8MHz crystal on the board at the moment, but I
also have a 4MHz in my junk box.

Wayne.

On Wednesday, September 25, 2013 1:57:07 AM UTC+10, Ants Pants wrote:
>
> HI Wayne,
>
> could you please tell us what is the frequency of you CPU clock oscillator
> can?
>
> Regards,
> Tony
>
>
> On Wed, Sep 25, 2013 at 1:18 AM, opticpow <wa...-***@public.gmane.org<javascript:>
> > wrote:
>
>> Hi Max,
>>
>> Attached is a high res of my board.
>>
>> 1. All jumpers are in the default positions, except for K6 & K8, as I'm
>> using Flash ROM (29F040)
>> 2. As above. Did double check
>> 3. I have two RAM chips, both identical (you can see one clearly in the
>> pic) both give the same result. I'd doubt both would be faulty / damaged?
>> 4. Done:
>>
>> start:
>> ld a,0ffh ; -> Put all ones in the accumulator
>> ld (8000h),a ; -> Store the contents of the accumulator at the
>> specified location
>> nop
>> nop
>>
>> ld a,(8000h) ; -> Load the contents of the specified memory
>> location in the accumulator
>> nop
>> nop
>> jp start ; -> Jump back to beginning if actual = expected
>> end
>>
>> 5. /WR is wiggling between 4.1 & 4.5MHz with the above code. I could not
>> see a CS on the schematic for the RAM chip, I did see /CS on pin 5 of the
>> DS1302. Is this what you mean? I see no activity on pin 5 with above
>> program running.
>>
>> Thanks for you help.
>>
>> Wayne.
>>
>>
>>
>> On Monday, September 23, 2013 8:44:54 PM UTC+10, Max Scane wrote:
>>
>>> Hi Wayne,
>>>
>>> 8000h is the first accessible ram address. Upon power on the ROM is
>>> switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
>>> 8000-FFFF. The test result looks like you can't access/write to the RAM.
>>>
>>> I would check the following:
>>>
>>> 1. Check RAM jumper
>>> 2. Check MCPL jumpers (set to default)
>>> 3. Replace RAM chip
>>> 4. Modify program to continuously loop reading/writing to RAM
>>> 5. Check with CRO or Logic probe for activity on the CS and /WR pins on
>>> the RAM
>>>
>>> Jumper settings can be found at:
>>> http://n8vem-sbc.pbworks.com/**w/page/39172478/N8VEM%20SBC%**
>>> 20V2%20Jumper%20Settings<http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings>
>>>
>>> I hope this helps.
>>>
>>> Regards,
>>>
>>> Max
>>>
>>>
>>>
>>> On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wa...-***@public.gmane.org> wrote:
>>>
>>>> Hi All,
>>>>
>>>> It has been a bit of a while (well long while actually) but life and
>>>> all that!
>>>>
>>>> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
>>>> debugging again. Current status is that scream works (lots of zeros). Next
>>>> test I've tried is this code (I believe John C suggested this):
>>>>
>>>> start:
>>>> ld a,0ffh ; -> Put all ones in the accumulator
>>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>>> the specified location
>>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>>> location in the accumulator
>>>> cp 0ffh ; -> Compare actual with expected
>>>> jp z,start ; -> Jump back to beginning if actual = expected
>>>> halt ; -> actual did not match expected so halt
>>>> end
>>>>
>>>>
>>>> Running this give me a Red Halt on the led, so I guess there is an
>>>> issue with the RAM. I've been studying the schematic, but I'm not quite
>>>> sure which of the chips would be required for this process. I'm guessing
>>>> not the extended addressing logic so maybe:
>>>>
>>>> U23 (obviously)
>>>> U21
>>>> and U4 U14 U6 from the IO decode logic??
>>>>
>>>> Thanks,
>>>>
>>>> Wayne.
>>>>
>>>> --
>>>> You received this message because you are subscribed to the Google
>>>> Groups "N8VEM" group.
>>>> To unsubscribe from this group and stop receiving emails from it, send
>>>> an email to n8vem+un...@**googlegroups.com.
>>>> To post to this group, send email to n8...-/JYPxA39Uh5TLH3MbocFF+G/***@public.gmane.org
>>>>
>>>> Visit this group at http://groups.google.com/**group/n8vem<http://groups.google.com/group/n8vem>
>>>> .
>>>> For more options, visit https://groups.google.com/**groups/opt_out<https://groups.google.com/groups/opt_out>
>>>> .
>>>>
>>>
>>> --
>> You received this message because you are subscribed to the Google Groups
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>>
>
>

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Ants Pants
2013-09-25 00:27:22 UTC
Permalink
Hi Wayne,

sorry i havent been following the messages closely but, just a point of
interest, i see you have a Z80 (not Z80A, or B, or D..etc) ( Z80 is
specified to run at 2.5Mhz) could this be an issue with your 8Mhz
oscillator?

Tony


On Wed, Sep 25, 2013 at 12:14 PM, opticpow <wayne-***@public.gmane.org> wrote:

> Hi Tony, I currently have a 8MHz crystal on the board at the moment, but I
> also have a 4MHz in my junk box.
>
> Wayne.
>
>
> On Wednesday, September 25, 2013 1:57:07 AM UTC+10, Ants Pants wrote:
>
>> HI Wayne,
>>
>> could you please tell us what is the frequency of you CPU clock
>> oscillator can?
>>
>> Regards,
>> Tony
>>
>>
>> On Wed, Sep 25, 2013 at 1:18 AM, opticpow <wa...-***@public.gmane.org> wrote:
>>
>>> Hi Max,
>>>
>>> Attached is a high res of my board.
>>>
>>> 1. All jumpers are in the default positions, except for K6 & K8, as I'm
>>> using Flash ROM (29F040)
>>> 2. As above. Did double check
>>> 3. I have two RAM chips, both identical (you can see one clearly in the
>>> pic) both give the same result. I'd doubt both would be faulty / damaged?
>>> 4. Done:
>>>
>>> start:
>>> ld a,0ffh ; -> Put all ones in the accumulator
>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>> the specified location
>>> nop
>>> nop
>>>
>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>> location in the accumulator
>>> nop
>>> nop
>>> jp start ; -> Jump back to beginning if actual = expected
>>> end
>>>
>>> 5. /WR is wiggling between 4.1 & 4.5MHz with the above code. I could not
>>> see a CS on the schematic for the RAM chip, I did see /CS on pin 5 of the
>>> DS1302. Is this what you mean? I see no activity on pin 5 with above
>>> program running.
>>>
>>> Thanks for you help.
>>>
>>> Wayne.
>>>
>>>
>>>
>>> On Monday, September 23, 2013 8:44:54 PM UTC+10, Max Scane wrote:
>>>
>>>> Hi Wayne,
>>>>
>>>> 8000h is the first accessible ram address. Upon power on the ROM is
>>>> switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
>>>> 8000-FFFF. The test result looks like you can't access/write to the RAM.
>>>>
>>>> I would check the following:
>>>>
>>>> 1. Check RAM jumper
>>>> 2. Check MCPL jumpers (set to default)
>>>> 3. Replace RAM chip
>>>> 4. Modify program to continuously loop reading/writing to RAM
>>>> 5. Check with CRO or Logic probe for activity on the CS and /WR pins on
>>>> the RAM
>>>>
>>>> Jumper settings can be found at:
>>>> http://n8vem-sbc.pbworks.com/**w**/page/39172478/N8VEM%20SBC%**20V**
>>>> 2%20Jumper%20Settings<http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings>
>>>>
>>>> I hope this helps.
>>>>
>>>> Regards,
>>>>
>>>> Max
>>>>
>>>>
>>>>
>>>> On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wa...-***@public.gmane.org> wrote:
>>>>
>>>>> Hi All,
>>>>>
>>>>> It has been a bit of a while (well long while actually) but life and
>>>>> all that!
>>>>>
>>>>> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
>>>>> debugging again. Current status is that scream works (lots of zeros). Next
>>>>> test I've tried is this code (I believe John C suggested this):
>>>>>
>>>>> start:
>>>>> ld a,0ffh ; -> Put all ones in the accumulator
>>>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>>>> the specified location
>>>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>>>> location in the accumulator
>>>>> cp 0ffh ; -> Compare actual with expected
>>>>> jp z,start ; -> Jump back to beginning if actual =
>>>>> expected
>>>>> halt ; -> actual did not match expected so halt
>>>>> end
>>>>>
>>>>>
>>>>> Running this give me a Red Halt on the led, so I guess there is an
>>>>> issue with the RAM. I've been studying the schematic, but I'm not quite
>>>>> sure which of the chips would be required for this process. I'm guessing
>>>>> not the extended addressing logic so maybe:
>>>>>
>>>>> U23 (obviously)
>>>>> U21
>>>>> and U4 U14 U6 from the IO decode logic??
>>>>>
>>>>> Thanks,
>>>>>
>>>>> Wayne.
>>>>>
>>>>> --
>>>>> You received this message because you are subscribed to the Google
>>>>> Groups "N8VEM" group.
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>>>>> an email to n8vem+un...@**googlegroups.com.
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>>>>> .
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>>>>> .
>>>>>
>>>>
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John Coffman
2013-09-25 00:44:06 UTC
Permalink
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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<head>
<meta content="text/html; charset=ISO-8859-1"
http-equiv="Content-Type">
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<body bgcolor="#ffffff" text="#000000">
Z84C0020PEC is a 20Mhz Z80.&nbsp; OK at lower frequencies, too.&nbsp; I use
this chip at 4Mhz, 8Mhz, 12Mhz.<br>
<br>
--John<br>
<br>
<br>
<br>
On 09/24/2013 05:27 PM, Ants Pants wrote:
<blockquote
cite="mid:CADCcKqPA4vLwZodkKhGhiE1k-=FQrMDTPPY4pkCqZmVROTjH1w-JsoAwUIsXosN+***@public.gmane.org"
type="cite">
<div dir="ltr">Hi Wayne,
<div><br>
</div>
<div>sorry i havent been following the messages closely but,
just a point of interest, i see you have a Z80 (not Z80A, or
B, or D..etc) ( Z80 is specified to run at 2.5Mhz) could this
be an issue with your 8Mhz oscillator?&nbsp;</div>
<div><br>
</div>
<div>Tony</div>
</div>
<div class="gmail_extra"><br>
<br>
<div class="gmail_quote">On Wed, Sep 25, 2013 at 12:14 PM,
opticpow <span dir="ltr">&lt;<a moz-do-not-send="true"
href="mailto:wayne-***@public.gmane.org" target="_blank">wayne-***@public.gmane.org</a>&gt;</span>
wrote:<br>
<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt
0.8ex; border-left: 1px solid rgb(204, 204, 204);
padding-left: 1ex;">
<div dir="ltr">Hi Tony, I currently have a 8MHz crystal on
the board at the moment, but I also have a 4MHz in my junk
box.<br>
<br>
Wayne.
<div class="im"><br>
<br>
On Wednesday, September 25, 2013 1:57:07 AM UTC+10, Ants
Pants wrote:</div>
<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt
0.8ex; border-left: 1px solid rgb(204, 204, 204);
padding-left: 1ex;">
<div class="im">
<div dir="ltr">HI Wayne,
<div><br>
</div>
<div>could you please tell us what is the frequency
of you CPU clock oscillator can?</div>
<div><br>
</div>
<div>Regards,</div>
<div>Tony</div>
</div>
</div>
<div>
<div class="h5">
<div><br>
<br>
<div class="gmail_quote">
On Wed, Sep 25, 2013 at 1:18 AM, opticpow <span
dir="ltr">&lt;<a moz-do-not-send="true">wa...-***@public.gmane.org</a>&gt;</span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:
0pt 0pt 0pt 0.8ex; border-left: 1px solid
rgb(204, 204, 204); padding-left: 1ex;">
<div dir="ltr">Hi Max,<br>
<br>
Attached is a high res of my board. <br>
<br>
1. All jumpers are in the default positions,
except for K6 &amp; K8, as I'm using Flash
ROM (29F040)<br>
2. As above. Did double check<br>
3. I have two RAM chips, both identical (you
can see one clearly in the pic) both give
the same result. I'd doubt both would be
faulty / damaged?<br>
4. Done:<br>
<br>
<div style="margin-left: 40px;"><font
size="1">
<div>start:<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,0ffh&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ; -&gt;
Put all ones in the accumulator<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; (8000h),a&nbsp;&nbsp; ; -&gt; Store
the contents of the accumulator at the
specified location<br>
</div>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; nop<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; nop
<div><br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,(8000h)&nbsp;&nbsp; ; -&gt; Load
the contents of the specified memory
location in the accumulator<br>
</div>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; nop<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; nop<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; jp&nbsp; start&nbsp;&nbsp;&nbsp;&nbsp; ; -&gt; Jump back
to beginning if actual = expected<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; end<br>
</font></div>
<br>
5. /WR is wiggling between 4.1 &amp; 4.5MHz
with the above code. I could not see a CS on
the schematic for the RAM chip, I did see
/CS on pin 5 of the DS1302. Is this what you
mean? I see no activity on pin 5 with above
program running.<br>
<br>
Thanks for you help.<br>
<br>
Wayne.
<div><br>
<br>
<br>
On Monday, September 23, 2013 8:44:54 PM
UTC+10, Max Scane wrote:</div>
<blockquote class="gmail_quote"
style="margin: 0pt 0pt 0pt 0.8ex;
border-left: 1px solid rgb(204, 204, 204);
padding-left: 1ex;">
<div dir="ltr">
<div>Hi Wayne,
<div><br>
</div>
<div>8000h is the first accessible ram
address. &nbsp;Upon power on the ROM is
switched into the first 32KB so you
have ROM at 0000-7FFF and RAM at
8000-FFFF. &nbsp;The test result looks
like you can't access/write to the
RAM.</div>
<div><br>
</div>
<div>I would check the following:</div>
<div><br>
</div>
<div>1. Check RAM jumper</div>
<div>2. Check MCPL jumpers &nbsp;(set to
default)</div>
<div>3. Replace RAM chip</div>
<div>4. Modify program to continuously
loop reading/writing to RAM</div>
<div>5. Check with CRO or Logic probe
for activity on the CS and /WR pins
on the RAM&nbsp;</div>
<div><br>
</div>
<div>Jumper settings can be found at:</div>
<div><a moz-do-not-send="true"
href="http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings"
target="_blank">http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings</a><br>
</div>
<div><br>
</div>
<div>I hope this helps.</div>
<div><br>
</div>
<div>Regards,</div>
<div><br>
</div>
<div>Max</div>
<div><br>
</div>
</div>
<div><br>
<br>
<div class="gmail_quote">
<div>On Mon, Sep 23, 2013 at 8:02
PM, opticpow <span dir="ltr">&lt;<a
moz-do-not-send="true">wa...-***@public.gmane.org</a>&gt;</span>
wrote:<br>
</div>
<blockquote class="gmail_quote"
style="margin: 0pt 0pt 0pt 0.8ex;
border-left: 1px solid rgb(204,
204, 204); padding-left: 1ex;">
<div>
<div dir="ltr">Hi All,<br>
<br>
It has been a bit of a while
(well long while actually) but
life and all that!<br>
<br>
Anyway, I have a new shed,
I've cracked out the the ol'
sbcv2 and I'm debugging again.
Current status is that scream
works (lots of zeros). Next
test I've tried is this code
(I believe John C suggested
this):<br>
<br>
start:<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,0ffh&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ;
-&gt; Put all ones in the
accumulator<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; (8000h),a&nbsp;&nbsp; ;
-&gt; Store the contents of
the accumulator at the
specified location<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,(8000h)&nbsp;&nbsp; ;
-&gt; Load the contents of the
specified memory location in
the accumulator<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cp&nbsp; 0ffh&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ;
-&gt; Compare actual with
expected<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; jp&nbsp; z,start&nbsp;&nbsp;&nbsp;&nbsp; ;
-&gt; Jump back to beginning
if actual = expected<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; halt&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ;
-&gt; actual did not match
expected so halt<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; end<br>
<br>
<br>
Running this give me a Red
Halt on the led, so I guess
there is an issue with the
RAM. I've been studying the
schematic, but I'm not quite
sure which of the chips would
be required for this process.
I'm guessing not the extended
addressing logic so maybe:<br>
<br>
U23 (obviously)<br>
U21<br>
and U4 U14 U6 from the IO
decode logic??<br>
<br>
Thanks,<br>
<br>
Wayne.<span><font
color="#888888"><br>
</font></span></div>
</div>
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Ants Pants
2013-09-25 00:52:43 UTC
Permalink
Ah yes,, i did not read the full part number Cmos, ok so we can rule that
out. :-)


On Wed, Sep 25, 2013 at 12:44 PM, John Coffman <johninsd-***@public.gmane.org> wrote:

> **
> Z84C0020PEC is a 20Mhz Z80. OK at lower frequencies, too. I use this
> chip at 4Mhz, 8Mhz, 12Mhz.
>
> --John
>
>
>
>
> On 09/24/2013 05:27 PM, Ants Pants wrote:
>
> Hi Wayne,
>
> sorry i havent been following the messages closely but, just a point of
> interest, i see you have a Z80 (not Z80A, or B, or D..etc) ( Z80 is
> specified to run at 2.5Mhz) could this be an issue with your 8Mhz
> oscillator?
>
> Tony
>
>
> On Wed, Sep 25, 2013 at 12:14 PM, opticpow <wayne-***@public.gmane.org> wrote:
>
>> Hi Tony, I currently have a 8MHz crystal on the board at the moment, but
>> I also have a 4MHz in my junk box.
>>
>> Wayne.
>>
>>
>> On Wednesday, September 25, 2013 1:57:07 AM UTC+10, Ants Pants wrote:
>>
>>> HI Wayne,
>>>
>>> could you please tell us what is the frequency of you CPU clock
>>> oscillator can?
>>>
>>> Regards,
>>> Tony
>>>
>>>
>>> On Wed, Sep 25, 2013 at 1:18 AM, opticpow <wa...-***@public.gmane.org> wrote:
>>>
>>>> Hi Max,
>>>>
>>>> Attached is a high res of my board.
>>>>
>>>> 1. All jumpers are in the default positions, except for K6 & K8, as I'm
>>>> using Flash ROM (29F040)
>>>> 2. As above. Did double check
>>>> 3. I have two RAM chips, both identical (you can see one clearly in the
>>>> pic) both give the same result. I'd doubt both would be faulty / damaged?
>>>> 4. Done:
>>>>
>>>> start:
>>>> ld a,0ffh ; -> Put all ones in the accumulator
>>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>>> the specified location
>>>> nop
>>>> nop
>>>>
>>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>>> location in the accumulator
>>>> nop
>>>> nop
>>>> jp start ; -> Jump back to beginning if actual = expected
>>>> end
>>>>
>>>> 5. /WR is wiggling between 4.1 & 4.5MHz with the above code. I could
>>>> not see a CS on the schematic for the RAM chip, I did see /CS on pin 5 of
>>>> the DS1302. Is this what you mean? I see no activity on pin 5 with above
>>>> program running.
>>>>
>>>> Thanks for you help.
>>>>
>>>> Wayne.
>>>>
>>>>
>>>>
>>>> On Monday, September 23, 2013 8:44:54 PM UTC+10, Max Scane wrote:
>>>>
>>>>> Hi Wayne,
>>>>>
>>>>> 8000h is the first accessible ram address. Upon power on the ROM is
>>>>> switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
>>>>> 8000-FFFF. The test result looks like you can't access/write to the RAM.
>>>>>
>>>>> I would check the following:
>>>>>
>>>>> 1. Check RAM jumper
>>>>> 2. Check MCPL jumpers (set to default)
>>>>> 3. Replace RAM chip
>>>>> 4. Modify program to continuously loop reading/writing to RAM
>>>>> 5. Check with CRO or Logic probe for activity on the CS and /WR pins
>>>>> on the RAM
>>>>>
>>>>> Jumper settings can be found at:
>>>>>
>>>>> http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings
>>>>>
>>>>> I hope this helps.
>>>>>
>>>>> Regards,
>>>>>
>>>>> Max
>>>>>
>>>>>
>>>>>
>>>>> On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wa...-***@public.gmane.org>wrote:
>>>>>
>>>>>> Hi All,
>>>>>>
>>>>>> It has been a bit of a while (well long while actually) but life and
>>>>>> all that!
>>>>>>
>>>>>> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
>>>>>> debugging again. Current status is that scream works (lots of zeros). Next
>>>>>> test I've tried is this code (I believe John C suggested this):
>>>>>>
>>>>>> start:
>>>>>> ld a,0ffh ; -> Put all ones in the accumulator
>>>>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>>>>> the specified location
>>>>>> ld a,(8000h) ; -> Load the contents of the specified
>>>>>> memory location in the accumulator
>>>>>> cp 0ffh ; -> Compare actual with expected
>>>>>> jp z,start ; -> Jump back to beginning if actual =
>>>>>> expected
>>>>>> halt ; -> actual did not match expected so halt
>>>>>> end
>>>>>>
>>>>>>
>>>>>> Running this give me a Red Halt on the led, so I guess there is an
>>>>>> issue with the RAM. I've been studying the schematic, but I'm not quite
>>>>>> sure which of the chips would be required for this process. I'm guessing
>>>>>> not the extended addressing logic so maybe:
>>>>>>
>>>>>> U23 (obviously)
>>>>>> U21
>>>>>> and U4 U14 U6 from the IO decode logic??
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>> Wayne.
>>>>>> --
>>>>>> You received this message because you are subscribed to the Google
>>>>>> Groups "N8VEM" group.
>>>>>> To unsubscribe from this group and stop receiving emails from it,
>>>>>> send an email to n8vem+un...-/JYPxA39Uh5TLH3MbocFF+G/***@public.gmane.org
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>>>>>>
>>>>>> Visit this group at http://groups.google.com/group/n8vem.
>>>>>> For more options, visit https://groups.google.com/groups/opt_out.
>>>>>>
>>>>>
>>>>> --
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opticpow
2013-09-25 01:00:10 UTC
Permalink
Thanks Tony for looking in to my issue.

John, that's good, I can rule out another thing.

I'll try Max's suggestions tonight when I get home.
Max Scane
2013-09-24 22:43:18 UTC
Permalink
Hi Wayne,

On the ram chip have a look at the following signals:

Pin 24 /OE This is the Output Enable, it is asserted during a read
Pin 22 /CS This is the Chip Select, it is asserted during an Read or Write
Pin 29 /WE This is the Write Enable, it is asserted during a Write

Another thing to look at is the DS1210 chip as it controls access to the
RAM chip.

Cheers!


On Tue, Sep 24, 2013 at 11:18 PM, opticpow <wayne-***@public.gmane.org> wrote:

> Hi Max,
>
> Attached is a high res of my board.
>
> 1. All jumpers are in the default positions, except for K6 & K8, as I'm
> using Flash ROM (29F040)
> 2. As above. Did double check
> 3. I have two RAM chips, both identical (you can see one clearly in the
> pic) both give the same result. I'd doubt both would be faulty / damaged?
> 4. Done:
>
> start:
> ld a,0ffh ; -> Put all ones in the accumulator
> ld (8000h),a ; -> Store the contents of the accumulator at the
> specified location
> nop
> nop
>
> ld a,(8000h) ; -> Load the contents of the specified memory
> location in the accumulator
> nop
> nop
> jp start ; -> Jump back to beginning if actual = expected
> end
>
> 5. /WR is wiggling between 4.1 & 4.5MHz with the above code. I could not
> see a CS on the schematic for the RAM chip, I did see /CS on pin 5 of the
> DS1302. Is this what you mean? I see no activity on pin 5 with above
> program running.
>
> Thanks for you help.
>
> Wayne.
>
>
>
> On Monday, September 23, 2013 8:44:54 PM UTC+10, Max Scane wrote:
>
>> Hi Wayne,
>>
>> 8000h is the first accessible ram address. Upon power on the ROM is
>> switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
>> 8000-FFFF. The test result looks like you can't access/write to the RAM.
>>
>> I would check the following:
>>
>> 1. Check RAM jumper
>> 2. Check MCPL jumpers (set to default)
>> 3. Replace RAM chip
>> 4. Modify program to continuously loop reading/writing to RAM
>> 5. Check with CRO or Logic probe for activity on the CS and /WR pins on
>> the RAM
>>
>> Jumper settings can be found at:
>> http://n8vem-sbc.pbworks.com/**w/page/39172478/N8VEM%20SBC%**
>> 20V2%20Jumper%20Settings<http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings>
>>
>> I hope this helps.
>>
>> Regards,
>>
>> Max
>>
>>
>>
>> On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wa...-***@public.gmane.org> wrote:
>>
>>> Hi All,
>>>
>>> It has been a bit of a while (well long while actually) but life and all
>>> that!
>>>
>>> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
>>> debugging again. Current status is that scream works (lots of zeros). Next
>>> test I've tried is this code (I believe John C suggested this):
>>>
>>> start:
>>> ld a,0ffh ; -> Put all ones in the accumulator
>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>> the specified location
>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>> location in the accumulator
>>> cp 0ffh ; -> Compare actual with expected
>>> jp z,start ; -> Jump back to beginning if actual = expected
>>> halt ; -> actual did not match expected so halt
>>> end
>>>
>>>
>>> Running this give me a Red Halt on the led, so I guess there is an issue
>>> with the RAM. I've been studying the schematic, but I'm not quite sure
>>> which of the chips would be required for this process. I'm guessing not the
>>> extended addressing logic so maybe:
>>>
>>> U23 (obviously)
>>> U21
>>> and U4 U14 U6 from the IO decode logic??
>>>
>>> Thanks,
>>>
>>> Wayne.
>>>
>>> --
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opticpow
2013-09-25 11:30:51 UTC
Permalink
Hi Max,

With that same program, here is a capture of those signals. What seems
interesting is that according to your description, shouldn't /OE be low, as
both /CE & /WE are asserted in the attached screenshot?

Wayne.

On Wednesday, September 25, 2013 8:43:18 AM UTC+10, Max Scane wrote:
>
> Hi Wayne,
>
> On the ram chip have a look at the following signals:
>
> Pin 24 /OE This is the Output Enable, it is asserted during a read
> Pin 22 /CS This is the Chip Select, it is asserted during an Read or Write
> Pin 29 /WE This is the Write Enable, it is asserted during a Write
>
> Another thing to look at is the DS1210 chip as it controls access to the
> RAM chip.
>
> Cheers!
>
>
> On Tue, Sep 24, 2013 at 11:18 PM, opticpow <wa...-***@public.gmane.org<javascript:>
> > wrote:
>
>> Hi Max,
>>
>> Attached is a high res of my board.
>>
>> 1. All jumpers are in the default positions, except for K6 & K8, as I'm
>> using Flash ROM (29F040)
>> 2. As above. Did double check
>> 3. I have two RAM chips, both identical (you can see one clearly in the
>> pic) both give the same result. I'd doubt both would be faulty / damaged?
>> 4. Done:
>>
>> start:
>> ld a,0ffh ; -> Put all ones in the accumulator
>> ld (8000h),a ; -> Store the contents of the accumulator at the
>> specified location
>> nop
>> nop
>>
>> ld a,(8000h) ; -> Load the contents of the specified memory
>> location in the accumulator
>> nop
>> nop
>> jp start ; -> Jump back to beginning if actual = expected
>> end
>>
>> 5. /WR is wiggling between 4.1 & 4.5MHz with the above code. I could not
>> see a CS on the schematic for the RAM chip, I did see /CS on pin 5 of the
>> DS1302. Is this what you mean? I see no activity on pin 5 with above
>> program running.
>>
>> Thanks for you help.
>>
>> Wayne.
>>
>>
>>
>> On Monday, September 23, 2013 8:44:54 PM UTC+10, Max Scane wrote:
>>
>>> Hi Wayne,
>>>
>>> 8000h is the first accessible ram address. Upon power on the ROM is
>>> switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
>>> 8000-FFFF. The test result looks like you can't access/write to the RAM.
>>>
>>> I would check the following:
>>>
>>> 1. Check RAM jumper
>>> 2. Check MCPL jumpers (set to default)
>>> 3. Replace RAM chip
>>> 4. Modify program to continuously loop reading/writing to RAM
>>> 5. Check with CRO or Logic probe for activity on the CS and /WR pins on
>>> the RAM
>>>
>>> Jumper settings can be found at:
>>> http://n8vem-sbc.pbworks.com/**w/page/39172478/N8VEM%20SBC%**
>>> 20V2%20Jumper%20Settings<http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings>
>>>
>>> I hope this helps.
>>>
>>> Regards,
>>>
>>> Max
>>>
>>>
>>>
>>> On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wa...-***@public.gmane.org> wrote:
>>>
>>>> Hi All,
>>>>
>>>> It has been a bit of a while (well long while actually) but life and
>>>> all that!
>>>>
>>>> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
>>>> debugging again. Current status is that scream works (lots of zeros). Next
>>>> test I've tried is this code (I believe John C suggested this):
>>>>
>>>> start:
>>>> ld a,0ffh ; -> Put all ones in the accumulator
>>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>>> the specified location
>>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>>> location in the accumulator
>>>> cp 0ffh ; -> Compare actual with expected
>>>> jp z,start ; -> Jump back to beginning if actual = expected
>>>> halt ; -> actual did not match expected so halt
>>>> end
>>>>
>>>>
>>>> Running this give me a Red Halt on the led, so I guess there is an
>>>> issue with the RAM. I've been studying the schematic, but I'm not quite
>>>> sure which of the chips would be required for this process. I'm guessing
>>>> not the extended addressing logic so maybe:
>>>>
>>>> U23 (obviously)
>>>> U21
>>>> and U4 U14 U6 from the IO decode logic??
>>>>
>>>> Thanks,
>>>>
>>>> Wayne.
>>>>
>>>> --
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>>>> Groups "N8VEM" group.
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>>>> an email to n8vem+un...@**googlegroups.com.
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>>>> For more options, visit https://groups.google.com/**groups/opt_out<https://groups.google.com/groups/opt_out>
>>>> .
>>>>
>>>
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Max Scane
2013-09-25 12:41:56 UTC
Permalink
Hi Wayne,

Well that is interesting. It looks like your write logic is working fine,
/CS and /WE are asserted at the same time which is correct.

However, the read logic seems to be incorrect. /CS and /OE should be
asserted at the same time much like the write sequence.

/CS enables the RAM chip and activates its address lines. When /OE goes
low the data from the RAM cells is put on the data bus. Without /CS, the
RAM won't do a thing.

The question now is why is /CS not asserted during a read of RAM. We know
that the read logic works for ROM because you can execute a program
correctly.

Looking at the schematic, if we work back from the RAM chip along the /CS
path, we have a DS1210. We know that is OK because we get /CS when writing.

Further back we have U15 (RAM/ROM Memory Decode Logic) this is where
/CS_RAM is generated).

/CS_RAM is generated when /MREQ , (Z80 signal saying we are doing a memory
operation rather than an IO operation) and A15 is high (8000h - FFFFh) or
when when /MREQ is asserted and the ROM is disabled.(RAM at 0-FFFF)

So at power up, ROM is enabled, therefore /CS_RAM will only be asserted
when we are doing a memory operation and the address is 8000h or above.

That sounds about right I think.

Still no explanation why you can't read from RAM though.

First things first.

1. Check your program, make sure you are writing to 8000h and not somewhere
else. The hex code should be 32 00 80.
2. Maybe try writing to other locations above 8000h.

I hope that makes sense (been a long day)
Let us know how you go with that.

Cheers!

Max










On Wed, Sep 25, 2013 at 9:30 PM, opticpow <wayne-***@public.gmane.org> wrote:

> Hi Max,
>
> With that same program, here is a capture of those signals. What seems
> interesting is that according to your description, shouldn't /OE be low, as
> both /CE & /WE are asserted in the attached screenshot?
>
> Wayne.
>
>
> On Wednesday, September 25, 2013 8:43:18 AM UTC+10, Max Scane wrote:
>
>> Hi Wayne,
>>
>> On the ram chip have a look at the following signals:
>>
>> Pin 24 /OE This is the Output Enable, it is asserted during a read
>> Pin 22 /CS This is the Chip Select, it is asserted during an Read or
>> Write
>> Pin 29 /WE This is the Write Enable, it is asserted during a Write
>>
>> Another thing to look at is the DS1210 chip as it controls access to the
>> RAM chip.
>>
>> Cheers!
>>
>>
>> On Tue, Sep 24, 2013 at 11:18 PM, opticpow <wa...-***@public.gmane.org> wrote:
>>
>>> Hi Max,
>>>
>>> Attached is a high res of my board.
>>>
>>> 1. All jumpers are in the default positions, except for K6 & K8, as I'm
>>> using Flash ROM (29F040)
>>> 2. As above. Did double check
>>> 3. I have two RAM chips, both identical (you can see one clearly in the
>>> pic) both give the same result. I'd doubt both would be faulty / damaged?
>>> 4. Done:
>>>
>>> start:
>>> ld a,0ffh ; -> Put all ones in the accumulator
>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>> the specified location
>>> nop
>>> nop
>>>
>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>> location in the accumulator
>>> nop
>>> nop
>>> jp start ; -> Jump back to beginning if actual = expected
>>> end
>>>
>>> 5. /WR is wiggling between 4.1 & 4.5MHz with the above code. I could not
>>> see a CS on the schematic for the RAM chip, I did see /CS on pin 5 of the
>>> DS1302. Is this what you mean? I see no activity on pin 5 with above
>>> program running.
>>>
>>> Thanks for you help.
>>>
>>> Wayne.
>>>
>>>
>>>
>>> On Monday, September 23, 2013 8:44:54 PM UTC+10, Max Scane wrote:
>>>
>>>> Hi Wayne,
>>>>
>>>> 8000h is the first accessible ram address. Upon power on the ROM is
>>>> switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
>>>> 8000-FFFF. The test result looks like you can't access/write to the RAM.
>>>>
>>>> I would check the following:
>>>>
>>>> 1. Check RAM jumper
>>>> 2. Check MCPL jumpers (set to default)
>>>> 3. Replace RAM chip
>>>> 4. Modify program to continuously loop reading/writing to RAM
>>>> 5. Check with CRO or Logic probe for activity on the CS and /WR pins on
>>>> the RAM
>>>>
>>>> Jumper settings can be found at:
>>>> http://n8vem-sbc.pbworks.com/**w**/page/39172478/N8VEM%20SBC%**20V**
>>>> 2%20Jumper%20Settings<http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings>
>>>>
>>>> I hope this helps.
>>>>
>>>> Regards,
>>>>
>>>> Max
>>>>
>>>>
>>>>
>>>> On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wa...-***@public.gmane.org> wrote:
>>>>
>>>>> Hi All,
>>>>>
>>>>> It has been a bit of a while (well long while actually) but life and
>>>>> all that!
>>>>>
>>>>> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
>>>>> debugging again. Current status is that scream works (lots of zeros). Next
>>>>> test I've tried is this code (I believe John C suggested this):
>>>>>
>>>>> start:
>>>>> ld a,0ffh ; -> Put all ones in the accumulator
>>>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>>>> the specified location
>>>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>>>> location in the accumulator
>>>>> cp 0ffh ; -> Compare actual with expected
>>>>> jp z,start ; -> Jump back to beginning if actual =
>>>>> expected
>>>>> halt ; -> actual did not match expected so halt
>>>>> end
>>>>>
>>>>>
>>>>> Running this give me a Red Halt on the led, so I guess there is an
>>>>> issue with the RAM. I've been studying the schematic, but I'm not quite
>>>>> sure which of the chips would be required for this process. I'm guessing
>>>>> not the extended addressing logic so maybe:
>>>>>
>>>>> U23 (obviously)
>>>>> U21
>>>>> and U4 U14 U6 from the IO decode logic??
>>>>>
>>>>> Thanks,
>>>>>
>>>>> Wayne.
>>>>>
>>>>> --
>>>>> You received this message because you are subscribed to the Google
>>>>> Groups "N8VEM" group.
>>>>> To unsubscribe from this group and stop receiving emails from it, send
>>>>> an email to n8vem+un...@**googlegroups.com.
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>>>>>
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>>>>> .
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>>>>> .
>>>>>
>>>>
>>>> --
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John Coffman
2013-09-25 19:14:45 UTC
Permalink
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html>
<head>
<meta content="text/html; charset=ISO-8859-1"
http-equiv="Content-Type">
<title></title>
</head>
<body bgcolor="#ffffff" text="#000000">
The /CS signal is /CS_RAM.&nbsp; The write /WR is to RAM.<br>
<br>
However, the /RD is the instruction fetch from ROM.&nbsp;&nbsp; The
instruction to store to 8000h is 3 bytes long.&nbsp; The /OE without
/CS_RAM is correct, since I take it your program is in ROM.&nbsp; /CS_ROM
should be asserted during these byte reads, not /CS_RAM, which is
the scope display.<br>
<br>
Move the /CS probe to /CS_ROM, and I bet you'll see the /CS on the
previous /OE pulses and not on the /WE pulse.<br>
<br>
--John<br>
<br>
<br>
<br>
<br>
<br>
On 09/25/2013 05:41 AM, Max Scane wrote:
<blockquote
cite="mid:CADv-vybnjVya+03qGt_-dZzcTx0Cdqm8SK0RFPY5_6vg=sh0zw-JsoAwUIsXosN+***@public.gmane.org"
type="cite">
<div dir="ltr">
<div>Hi Wayne,</div>
<div><br>
</div>
Well that is interesting. &nbsp;It looks like your write logic is
working fine, /CS and /WE are asserted at the same time which is
correct.
<div><br>
</div>
<div>However, the read logic seems to be incorrect. &nbsp;/CS and /OE
should be asserted at the same time much like the write
sequence.</div>
<div><br>
</div>
<div>/CS enables the RAM chip and activates its address lines.
&nbsp;When /OE goes low the data from the RAM cells is put on the
data bus. &nbsp;Without /CS, the RAM won't do a thing.</div>
<div><br>
</div>
<div>The question now is why is /CS not asserted during a read
of RAM. &nbsp;We know that the read logic works for ROM because you
can execute a program</div>
<div>&nbsp;correctly.<br>
</div>
<div><br>
</div>
<div>Looking at the schematic, if we work back from the RAM chip
along the /CS path, we have a DS1210. &nbsp;We know that is OK
because we get /CS when writing.</div>
<div><br>
</div>
<div>
Further back we have U15 (RAM/ROM Memory Decode Logic) &nbsp;this
is where /CS_RAM is generated). &nbsp;</div>
<div><br>
</div>
<div>/CS_RAM is generated when /MREQ , (Z80 signal saying we are
doing a memory operation rather than an IO operation) and A15
is high (8000h - FFFFh) &nbsp; or &nbsp; when when /MREQ is asserted and
the ROM is disabled.(RAM at 0-FFFF)</div>
<div><br>
</div>
<div>So at power up, ROM is enabled, therefore /CS_RAM will only
be asserted when we are doing a memory operation and the
address is 8000h or above.</div>
<div><br>
</div>
<div>That sounds about right I think.</div>
<div><br>
</div>
<div>Still no explanation why you can't read from RAM though.</div>
<div><br>
</div>
<div>First things first.</div>
<div><br>
</div>
<div>1. Check your program, make sure you are writing to 8000h
and not somewhere else. &nbsp;The hex code should be 32 00 80.</div>
<div>2. Maybe try writing to other locations above 8000h.</div>
<div><br>
</div>
<div>I hope that makes sense (been a long day)</div>
<div>Let us know how you go with that.</div>
<div><br>
</div>
<div>Cheers!</div>
<div><br>
</div>
<div>Max</div>
<div><br>
</div>
<div><br>
</div>
<div><br>
</div>
<div><br>
</div>
<div><br>
</div>
<div><br>
</div>
<div><br>
</div>
<div><br>
</div>
</div>
<div class="gmail_extra"><br>
<br>
<div class="gmail_quote">On Wed, Sep 25, 2013 at 9:30 PM,
opticpow <span dir="ltr">&lt;<a moz-do-not-send="true"
href="mailto:wayne-***@public.gmane.org" target="_blank">wayne-***@public.gmane.org</a>&gt;</span>
wrote:<br>
<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt
0.8ex; border-left: 1px solid rgb(204, 204, 204);
padding-left: 1ex;">
<div dir="ltr">Hi Max,<br>
<br>
With that same program, here is a capture of those
signals. What seems interesting is that according to your
description, shouldn't /OE be low, as both /CE &amp; /WE
are asserted in the attached screenshot?<br>
<br>
Wayne.
<div class="im"><br>
<br>
On Wednesday, September 25, 2013 8:43:18 AM UTC+10, Max
Scane wrote:</div>
<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt
0.8ex; border-left: 1px solid rgb(204, 204, 204);
padding-left: 1ex;">
<div dir="ltr">
Hi Wayne,
<div><br>
</div>
<div class="im">
<div>On the ram chip have a look at the following
signals:</div>
<div><br>
</div>
<div>Pin 24 /OE &nbsp;This is the Output Enable, it is
asserted during a read</div>
<div>Pin 22 /CS &nbsp;This is the Chip Select, it is
asserted during an Read or Write</div>
<div>Pin 29 /WE &nbsp;This is the Write Enable, it is
asserted during a Write</div>
<div><br>
</div>
<div>Another thing to look at is the DS1210 chip as
it controls access to the RAM chip.</div>
<div><br>
</div>
<div>Cheers!</div>
</div>
</div>
<div>
<div class="h5">
<div><br>
<br>
<div class="gmail_quote">On Tue, Sep 24, 2013 at
11:18 PM, opticpow <span dir="ltr">&lt;<a
moz-do-not-send="true">wa...-***@public.gmane.org</a>&gt;</span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:
0pt 0pt 0pt 0.8ex; border-left: 1px solid
rgb(204, 204, 204); padding-left: 1ex;">
<div dir="ltr">Hi Max,<br>
<br>
Attached is a high res of my board. <br>
<br>
1. All jumpers are in the default positions,
except for K6 &amp; K8, as I'm using Flash
ROM (29F040)<br>
2. As above. Did double check<br>
3. I have two RAM chips, both identical (you
can see one clearly in the pic) both give
the same result. I'd doubt both would be
faulty / damaged?<br>
4. Done:<br>
<br>
<div style="margin-left: 40px;"><font
size="1">
<div>start:<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,0ffh&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ; -&gt;
Put all ones in the accumulator<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; (8000h),a&nbsp;&nbsp; ; -&gt; Store
the contents of the accumulator at the
specified location<br>
</div>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; nop<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; nop
<div><br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,(8000h)&nbsp;&nbsp; ; -&gt; Load
the contents of the specified memory
location in the accumulator<br>
</div>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; nop<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; nop<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; jp&nbsp; start&nbsp;&nbsp;&nbsp;&nbsp; ; -&gt; Jump back
to beginning if actual = expected<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; end<br>
</font></div>
<br>
5. /WR is wiggling between 4.1 &amp; 4.5MHz
with the above code. I could not see a CS on
the schematic for the RAM chip, I did see
/CS on pin 5 of the DS1302. Is this what you
mean? I see no activity on pin 5 with above
program running.<br>
<br>
Thanks for you help.<br>
<br>
Wayne.
<div><br>
<br>
<br>
On Monday, September 23, 2013 8:44:54 PM
UTC+10, Max Scane wrote:</div>
<blockquote class="gmail_quote"
style="margin: 0pt 0pt 0pt 0.8ex;
border-left: 1px solid rgb(204, 204, 204);
padding-left: 1ex;">
<div dir="ltr">
<div>Hi Wayne,
<div><br>
</div>
<div>8000h is the first accessible ram
address. &nbsp;Upon power on the ROM is
switched into the first 32KB so you
have ROM at 0000-7FFF and RAM at
8000-FFFF. &nbsp;The test result looks
like you can't access/write to the
RAM.</div>
<div><br>
</div>
<div>I would check the following:</div>
<div><br>
</div>
<div>1. Check RAM jumper</div>
<div>2. Check MCPL jumpers &nbsp;(set to
default)</div>
<div>3. Replace RAM chip</div>
<div>4. Modify program to continuously
loop reading/writing to RAM</div>
<div>5. Check with CRO or Logic probe
for activity on the CS and /WR pins
on the RAM&nbsp;</div>
<div><br>
</div>
<div>Jumper settings can be found at:</div>
<div><a moz-do-not-send="true"
href="http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings"
target="_blank">http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings</a><br>
</div>
<div><br>
</div>
<div>I hope this helps.</div>
<div><br>
</div>
<div>Regards,</div>
<div><br>
</div>
<div>Max</div>
<div><br>
</div>
</div>
<div><br>
<br>
<div class="gmail_quote">
<div>On Mon, Sep 23, 2013 at 8:02
PM, opticpow <span dir="ltr">&lt;<a
moz-do-not-send="true">wa...-***@public.gmane.org</a>&gt;</span>
wrote:<br>
</div>
<blockquote class="gmail_quote"
style="margin: 0pt 0pt 0pt 0.8ex;
border-left: 1px solid rgb(204,
204, 204); padding-left: 1ex;">
<div>
<div dir="ltr">Hi All,<br>
<br>
It has been a bit of a while
(well long while actually) but
life and all that!<br>
<br>
Anyway, I have a new shed,
I've cracked out the the ol'
sbcv2 and I'm debugging again.
Current status is that scream
works (lots of zeros). Next
test I've tried is this code
(I believe John C suggested
this):<br>
<br>
start:<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,0ffh&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ;
-&gt; Put all ones in the
accumulator<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; (8000h),a&nbsp;&nbsp; ;
-&gt; Store the contents of
the accumulator at the
specified location<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,(8000h)&nbsp;&nbsp; ;
-&gt; Load the contents of the
specified memory location in
the accumulator<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cp&nbsp; 0ffh&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ;
-&gt; Compare actual with
expected<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; jp&nbsp; z,start&nbsp;&nbsp;&nbsp;&nbsp; ;
-&gt; Jump back to beginning
if actual = expected<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; halt&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ;
-&gt; actual did not match
expected so halt<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; end<br>
<br>
<br>
Running this give me a Red
Halt on the led, so I guess
there is an issue with the
RAM. I've been studying the
schematic, but I'm not quite
sure which of the chips would
be required for this process.
I'm guessing not the extended
addressing logic so maybe:<br>
<br>
U23 (obviously)<br>
U21<br>
and U4 U14 U6 from the IO
decode logic??<br>
<br>
Thanks,<br>
<br>
Wayne.<span><font
color="#888888"><br>
</font></span></div>
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Max Scane
2013-09-25 21:55:37 UTC
Permalink
Hi John,

Yes you are right. I forgot about the instruction fetch following the
write. The program did include a read from the RAM so the 4th assertion of
/RD after the write should have had an assertion of /OE as well.

Wayne, perhaps, you can look for this combination as well. That will prove
read access to RAM is OK.


Well it was in interesting excursion through the logic anyway!

Cheers!


On Thu, Sep 26, 2013 at 5:14 AM, John Coffman <johninsd-***@public.gmane.org> wrote:

> **
> The /CS signal is /CS_RAM. The write /WR is to RAM.
>
> However, the /RD is the instruction fetch from ROM. The instruction to
> store to 8000h is 3 bytes long. The /OE without /CS_RAM is correct, since
> I take it your program is in ROM. /CS_ROM should be asserted during these
> byte reads, not /CS_RAM, which is the scope display.
>
> Move the /CS probe to /CS_ROM, and I bet you'll see the /CS on the
> previous /OE pulses and not on the /WE pulse.
>
> --John
>
>
>
>
>
>
> On 09/25/2013 05:41 AM, Max Scane wrote:
>
> Hi Wayne,
>
> Well that is interesting. It looks like your write logic is working
> fine, /CS and /WE are asserted at the same time which is correct.
>
> However, the read logic seems to be incorrect. /CS and /OE should be
> asserted at the same time much like the write sequence.
>
> /CS enables the RAM chip and activates its address lines. When /OE goes
> low the data from the RAM cells is put on the data bus. Without /CS, the
> RAM won't do a thing.
>
> The question now is why is /CS not asserted during a read of RAM. We
> know that the read logic works for ROM because you can execute a program
> correctly.
>
> Looking at the schematic, if we work back from the RAM chip along the
> /CS path, we have a DS1210. We know that is OK because we get /CS when
> writing.
>
> Further back we have U15 (RAM/ROM Memory Decode Logic) this is where
> /CS_RAM is generated).
>
> /CS_RAM is generated when /MREQ , (Z80 signal saying we are doing a
> memory operation rather than an IO operation) and A15 is high (8000h -
> FFFFh) or when when /MREQ is asserted and the ROM is disabled.(RAM at
> 0-FFFF)
>
> So at power up, ROM is enabled, therefore /CS_RAM will only be asserted
> when we are doing a memory operation and the address is 8000h or above.
>
> That sounds about right I think.
>
> Still no explanation why you can't read from RAM though.
>
> First things first.
>
> 1. Check your program, make sure you are writing to 8000h and not
> somewhere else. The hex code should be 32 00 80.
> 2. Maybe try writing to other locations above 8000h.
>
> I hope that makes sense (been a long day)
> Let us know how you go with that.
>
> Cheers!
>
> Max
>
>
>
>
>
>
>
>
>
>
> On Wed, Sep 25, 2013 at 9:30 PM, opticpow <wayne-***@public.gmane.org> wrote:
>
>> Hi Max,
>>
>> With that same program, here is a capture of those signals. What seems
>> interesting is that according to your description, shouldn't /OE be low, as
>> both /CE & /WE are asserted in the attached screenshot?
>>
>> Wayne.
>>
>>
>> On Wednesday, September 25, 2013 8:43:18 AM UTC+10, Max Scane wrote:
>>
>>> Hi Wayne,
>>>
>>> On the ram chip have a look at the following signals:
>>>
>>> Pin 24 /OE This is the Output Enable, it is asserted during a read
>>> Pin 22 /CS This is the Chip Select, it is asserted during an Read or
>>> Write
>>> Pin 29 /WE This is the Write Enable, it is asserted during a Write
>>>
>>> Another thing to look at is the DS1210 chip as it controls access to
>>> the RAM chip.
>>>
>>> Cheers!
>>>
>>>
>>> On Tue, Sep 24, 2013 at 11:18 PM, opticpow <wa...-***@public.gmane.org> wrote:
>>>
>>>> Hi Max,
>>>>
>>>> Attached is a high res of my board.
>>>>
>>>> 1. All jumpers are in the default positions, except for K6 & K8, as I'm
>>>> using Flash ROM (29F040)
>>>> 2. As above. Did double check
>>>> 3. I have two RAM chips, both identical (you can see one clearly in the
>>>> pic) both give the same result. I'd doubt both would be faulty / damaged?
>>>> 4. Done:
>>>>
>>>> start:
>>>> ld a,0ffh ; -> Put all ones in the accumulator
>>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>>> the specified location
>>>> nop
>>>> nop
>>>>
>>>> ld a,(8000h) ; -> Load the contents of the specified memory
>>>> location in the accumulator
>>>> nop
>>>> nop
>>>> jp start ; -> Jump back to beginning if actual = expected
>>>> end
>>>>
>>>> 5. /WR is wiggling between 4.1 & 4.5MHz with the above code. I could
>>>> not see a CS on the schematic for the RAM chip, I did see /CS on pin 5 of
>>>> the DS1302. Is this what you mean? I see no activity on pin 5 with above
>>>> program running.
>>>>
>>>> Thanks for you help.
>>>>
>>>> Wayne.
>>>>
>>>>
>>>>
>>>> On Monday, September 23, 2013 8:44:54 PM UTC+10, Max Scane wrote:
>>>>
>>>>> Hi Wayne,
>>>>>
>>>>> 8000h is the first accessible ram address. Upon power on the ROM is
>>>>> switched into the first 32KB so you have ROM at 0000-7FFF and RAM at
>>>>> 8000-FFFF. The test result looks like you can't access/write to the RAM.
>>>>>
>>>>> I would check the following:
>>>>>
>>>>> 1. Check RAM jumper
>>>>> 2. Check MCPL jumpers (set to default)
>>>>> 3. Replace RAM chip
>>>>> 4. Modify program to continuously loop reading/writing to RAM
>>>>> 5. Check with CRO or Logic probe for activity on the CS and /WR pins
>>>>> on the RAM
>>>>>
>>>>> Jumper settings can be found at:
>>>>>
>>>>> http://n8vem-sbc.pbworks.com/w/page/39172478/N8VEM%20SBC%20V2%20Jumper%20Settings
>>>>>
>>>>> I hope this helps.
>>>>>
>>>>> Regards,
>>>>>
>>>>> Max
>>>>>
>>>>>
>>>>>
>>>>> On Mon, Sep 23, 2013 at 8:02 PM, opticpow <wa...-***@public.gmane.org>wrote:
>>>>>
>>>>>> Hi All,
>>>>>>
>>>>>> It has been a bit of a while (well long while actually) but life and
>>>>>> all that!
>>>>>>
>>>>>> Anyway, I have a new shed, I've cracked out the the ol' sbcv2 and I'm
>>>>>> debugging again. Current status is that scream works (lots of zeros). Next
>>>>>> test I've tried is this code (I believe John C suggested this):
>>>>>>
>>>>>> start:
>>>>>> ld a,0ffh ; -> Put all ones in the accumulator
>>>>>> ld (8000h),a ; -> Store the contents of the accumulator at
>>>>>> the specified location
>>>>>> ld a,(8000h) ; -> Load the contents of the specified
>>>>>> memory location in the accumulator
>>>>>> cp 0ffh ; -> Compare actual with expected
>>>>>> jp z,start ; -> Jump back to beginning if actual =
>>>>>> expected
>>>>>> halt ; -> actual did not match expected so halt
>>>>>> end
>>>>>>
>>>>>>
>>>>>> Running this give me a Red Halt on the led, so I guess there is an
>>>>>> issue with the RAM. I've been studying the schematic, but I'm not quite
>>>>>> sure which of the chips would be required for this process. I'm guessing
>>>>>> not the extended addressing logic so maybe:
>>>>>>
>>>>>> U23 (obviously)
>>>>>> U21
>>>>>> and U4 U14 U6 from the IO decode logic??
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>> Wayne.
>>>>>> --
>>>>>> You received this message because you are subscribed to the Google
>>>>>> Groups "N8VEM" group.
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>>>>>> send an email to n8vem+un...-/JYPxA39Uh5TLH3MbocFF+G/***@public.gmane.org
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>>>>>
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opticpow
2013-09-26 10:14:36 UTC
Permalink
Hi Max & John,

I have decided to so a single shot run and record the whole shebang. Here
is the code:

start:
ld a,0ffh ; -> Put all ones in the accumulator
ld (8000h),a ; -> Store the contents of the accumulator at the
specified location
ld a,(8000h) ; -> Load the contents of the specified memory
location in the accumulator
halt
end

Attached is a paste us of the whole run, which by my calcs from reset to
halt is approx 4.9usec

The read from ROM appears to match the /CS_ROM by my understanding. Should
there be a signal that is aserted when reading from RAM, just like the
write?

Thanks,

Wayne.

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p***@public.gmane.org
2013-09-26 13:09:25 UTC
Permalink
Hi Wayne,

The /CS_RAM signal is asserted twice: write and then read. You can see the difference by looking at the /OE and /WE signals. When writing, /OE is deasserted and /WE is asserted. When reading, /OE is asserted and /WE is deasserted. In general, your timing diagram looks good.

One side note - can you check whether your memory-paging hardware is properly reset after boot (U12 & U13 outputs are all 0's). One more thought - depending on jumpers K10 & K11, the memory paging layout is changing from 32K-32K to 48K-16K, so it's possible for address 0x8000 to be mapped to a ROM location.

Regards,
picmaster


> The read from ROM appears to match the /CS_ROM by my understanding. Should
> there be a signal that is aserted when reading from RAM, just like the
> write?


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John Coffman
2013-09-26 18:13:45 UTC
Permalink
opticpow
2013-09-30 11:33:11 UTC
Permalink
Hi John,

I've done some more testing, and I've buzzed out the both the data and
address lines, and all was good. I also ordered a new DS1210 before I went
away and it arrived today, so I tried that too, no avail. The testmem
program still fails the compare and halts.

Next I'll try monitoring the data lines to see what I can see.

Wayne.

On Friday, September 27, 2013 4:13:45 AM UTC+10, John Coffman wrote:
>
> I attach an annotated copy of your signal trace.
>
> I'd say the signals are exactly correct.
>
> Check paging jumpers; data direction driver; data lines. Put the /RESET
> or /HALT probe on Data Pins, DATA_DIR. Check the Data lines at the CPU and
> at the RAM chip. If paging jumpers are okay, there may be a bad PC board
> trace between the CPU and RAM -- check by removing CPU, ROM, RAM and using
> an ohmmeter to check data line continuity. Continuity is Okay between CPU
> and ROM.
>
> --John
>
>
>
>
> On 09/26/2013 03:14 AM, opticpow wrote:
>
>
> Hi Max & John,
>
> I have decided to so a single shot run and record the whole shebang. Here
> is the code:
>
> start:
> ld a,0ffh ; -> Put all ones in the accumulator
> ld (8000h),a ; -> Store the contents of the accumulator at the
> specified location
> ld a,(8000h) ; -> Load the contents of the specified memory
> location in the accumulator
> halt
> end
>
> Attached is a paste us of the whole run, which by my calcs from reset to
> halt is approx 4.9usec
>
> The read from ROM appears to match the /CS_ROM by my understanding. Should
> there be a signal that is aserted when reading from RAM, just like the
> write?
>
> Thanks,
>
> Wayne.
>
> --
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oscarv
2013-09-30 13:48:54 UTC
Permalink
Hi,

At the risk of saying something rather obvious - did you either insert
batteries or disable the DS1210?

Here's the thing I discovered with my Zeta: when it was powered up but no
battery was attached this came into play... (taken from the data sheet):

*The fourth function the DS1210 performs is a battery status warning so
that potential data loss is avoided.*
*Each time that the circuit is powered up the battery voltage is checked
with a precision comparator. If the*
*battery voltage is less than 2.0 volts, the second memory cycle is
inhibited. Battery status can, therefore,*
*be determined by performing a read cycle after power - up to any location
in memory, verifying that*
*memory location content. A subsequent write cycle can then be executed to
the same memory location*
*altering the data. If the next read cycle fails to verify the written
data, then the batteries are less than 2.0V**
and data is in danger of being corrupted.*

So, by not inserting the battery but enabling the DS1210, my Zeta would run
anything between a few cycles and a few seconds before crashing on the
battery-low action of the DS1210.

Long shot, but may this be related to your problem?

Regards,

Oscar.


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John Coffman
2013-10-01 00:40:51 UTC
Permalink
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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<head>
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Both the battery inputs MUST be grounded if the 1210 is not in use.<br>
<br>
OR&nbsp; pull the 1210 and short pins 1-8 and 5-6.&nbsp; I ran this way for
some time before I acquired a 1210.<br>
<br>
--John<br>
<br>
<br>
<br>
On 09/30/2013 06:48 AM, oscarv wrote:
<blockquote
cite="mid:f4ae9375-d4a7-4556-ac31-80f4d9c71048-/***@public.gmane.org"
type="cite">
<div dir="ltr">Hi,<br>
<br>
At the risk of saying something rather obvious - did you either
insert batteries or disable the DS1210?<br>
<br>
Here's the thing I discovered with my Zeta: when it was powered
up but no battery was attached this came into play... (taken
from the data sheet):<br>
<br>
<div style="margin-left: 40px;"><i>The fourth function the
DS1210 performs is a battery status warning so that
potential data loss is avoided.</i><br>
<i>Each time that the circuit is powered up the battery
voltage is checked with a precision comparator. If the</i><br>
<i>battery voltage is less than 2.0 volts, <b>the second
memory cycle is inhibited. </b>Battery status can,
therefore,</i><br>
<i>be determined by performing a read cycle after power - up
to any location in memory, verifying that</i><br>
<i>memory location content. A subsequent write cycle can then
be executed to the same memory location</i><br>
<i>altering the data.<b> If the next read cycle fails to
verify the written data, then the batteries are less than
2.0V</b></i><b><br>
<i>and data is in danger of being corrupted.</i></b><br>
<br>
</div>
So, by not inserting the battery but enabling the DS1210, my
Zeta would run anything between a few cycles and a few seconds
before crashing on the battery-low action of the DS1210. <br>
<br>
Long shot, but may this be related to your problem?<br>
<br>
Regards,<br>
<br>
Oscar.<br>
<br>
<br>
</div>
</blockquote>
</body>
</html>

<p></p>

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Douglas Goodall
2013-09-30 22:46:46 UTC
Permalink
Wayne,

I agree the next step is to monitor the data lines as well so you can verify that
the data coming back was as written. This is where having enough logic
analyzer channels becomes so important. I agree with John, the signals look
right to me also. The next capture should be very interesting. I would try it
first with FF then with 00 to make sure what you are reading back is really
what you wrote and not an empty buss.

Douglas

On Sep 30, 2013, at 4:33 AM, opticpow <wayne-***@public.gmane.org> wrote:

> Hi John,
>
> I've done some more testing, and I've buzzed out the both the data and address lines, and all was good. I also ordered a new DS1210 before I went away and it arrived today, so I tried that too, no avail. The testmem program still fails the compare and halts.
>
> Next I'll try monitoring the data lines to see what I can see.
>
> Wayne.
>
> On Friday, September 27, 2013 4:13:45 AM UTC+10, John Coffman wrote:
> I attach an annotated copy of your signal trace.
>
> I'd say the signals are exactly correct.
>
> Check paging jumpers; data direction driver; data lines. Put the /RESET or /HALT probe on Data Pins, DATA_DIR. Check the Data lines at the CPU and at the RAM chip. If paging jumpers are okay, there may be a bad PC board trace between the CPU and RAM -- check by removing CPU, ROM, RAM and using an ohmmeter to check data line continuity. Continuity is Okay between CPU and ROM.
>
> --John
>
>
>
>
> On 09/26/2013 03:14 AM, opticpow wrote:
>>
>>
>> Hi Max & John,
>>
>> I have decided to so a single shot run and record the whole shebang. Here is the code:
>>
>> start:
>> ld a,0ffh ; -> Put all ones in the accumulator
>> ld (8000h),a ; -> Store the contents of the accumulator at the specified location
>> ld a,(8000h) ; -> Load the contents of the specified memory location in the accumulator
>> halt
>> end
>>
>> Attached is a paste us of the whole run, which by my calcs from reset to halt is approx 4.9usec
>>
>> The read from ROM appears to match the /CS_ROM by my understanding. Should there be a signal that is aserted when reading from RAM, just like the write?
>>
>> Thanks,
>>
>> Wayne.
>>
>> --
>> You received this message because you are subscribed to the Google Groups "N8VEM" group.
>> To unsubscribe from this group and stop receiving emails from it, send an email to n8vem+un...-/JYPxA39Uh5TLH3MbocFF+G/***@public.gmane.org
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>
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doug-***@public.gmane.org
http://goodall.us.com
WQRLl515

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John Coffman
2013-10-01 00:47:33 UTC
Permalink
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Wayne,<br>
<br>
What a puzzle.<br>
<br>
All those signals look good at the test points.&nbsp; Are they good at
all points they route to?&nbsp; (more buzzing traces)<br>
<br>
A bad RAM chip could also explain the problem.&nbsp; Use you logic probe
to check each data bit to see if the correct value is going to RAM
and coming back correctly to the Z80.<br>
<br>
I'd say the data path from EPROM to CPU is good, because it looks
like the CPU is executing the instructions correctly.<br>
<br>
But look at the 1210 first!&nbsp; (see my earlier reply).<br>
<br>
--John<br>
<br>
<br>
<br>
<br>
<br>
On 09/30/2013 04:33 AM, opticpow wrote:
<blockquote
cite="mid:9101f2e7-c92e-4333-b450-0a545fc1d121-/***@public.gmane.org"
type="cite">
<div dir="ltr">Hi John,<br>
<br>
I've done some more testing, and I've buzzed out the both the
data and address lines, and all was good. I also ordered a new
DS1210 before I went away and it arrived today, so I tried that
too, no avail. The testmem program still fails the compare and
halts. <br>
<br>
Next I'll try monitoring the data lines to see what I can see.<br>
<br>
Wayne.<br>
<br>
On Friday, September 27, 2013 4:13:45 AM UTC+10, John Coffman
wrote:
<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt
0.8ex; border-left: 1px solid rgb(204, 204, 204);
padding-left: 1ex;">
<div bgcolor="#ffffff" text="#000000"> I attach an annotated
copy of your signal trace.<br>
<br>
I'd say the signals are exactly correct.<br>
<br>
Check paging jumpers; data direction driver; data lines.&nbsp;
Put the /RESET or /HALT probe on Data Pins, DATA_DIR.&nbsp; Check
the Data lines at the CPU and at the RAM chip.&nbsp; If paging
jumpers are okay, there may be a bad PC board trace between
the CPU and RAM -- check by removing CPU, ROM, RAM and using
an ohmmeter to check data line continuity.&nbsp; Continuity is
Okay between CPU and ROM.<br>
<br>
--John<br>
<br>
<br>
<br>
<br>
On 09/26/2013 03:14 AM, opticpow wrote:
<blockquote type="cite">
<div dir="ltr"><br>
Hi Max &amp; John,<br>
<br>
I have decided to so a single shot run and record the
whole shebang. Here is the code:<br>
<font size="1"><span style="font-family: courier
new,monospace;"><br>
</span></font>
<div style="margin-left: 40px;"><font size="1"><span
style="font-family: courier new,monospace;">start:</span></font><br>
<font size="1"><span style="font-family: courier
new,monospace;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,0ffh&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ;
-&gt; Put all ones in the accumulator</span></font><br>
<font size="1"><span style="font-family: courier
new,monospace;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; (8000h),a&nbsp;&nbsp; ; -&gt;
Store the contents of the accumulator at the
specified location</span></font><br>
<font size="1"><span style="font-family: courier
new,monospace;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ld&nbsp; a,(8000h)&nbsp;&nbsp; ; -&gt;
Load the contents of the specified memory location
in the accumulator</span></font><br>
<font size="1"><span style="font-family: courier
new,monospace;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; halt</span></font><br>
<font size="1"><span style="font-family: courier
new,monospace;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; end</span></font></div>
<br>
<font face="arial,sans-serif">Attached is a paste us of
the whole run, which by my calcs from reset to halt is
approx 4.9usec<br>
<br>
The read from ROM appears to match the /CS_ROM by my
understanding. Should there be a signal that is
aserted when reading from RAM, just like the write?<br>
<br>
Thanks,<br>
<br>
Wayne.<br>
</font><br>
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opticpow
2013-10-01 10:42:50 UTC
Permalink
Ok, WOW...um WOW.

First Wow cause I now have a working board. Second Wow for how something so
simple has been critical to getting a working board.

This issue was the DS1210. I have pulled it as jumpered as per John's
message and that solved the problem. A BIG thanks to Oscar, John, Max &
Doug for all the help.

I have two questions:

1. Did I miss some instruction somewhere that describes how the battery &
DS1210 works? How did everyone else not have the same issue???
2. I'm still a little lost as to what jumpers / inputs I need to ground
when the DS1210 is in circuit? I'm aware of JP1. Is BT1 related?

Thanks,

Wayne.

On Tuesday, October 1, 2013 10:47:33 AM UTC+10, John Coffman wrote:
>
> Wayne,
>
> What a puzzle.
>
> All those signals look good at the test points. Are they good at all
> points they route to? (more buzzing traces)
>
> A bad RAM chip could also explain the problem. Use you logic probe to
> check each data bit to see if the correct value is going to RAM and coming
> back correctly to the Z80.
>
> I'd say the data path from EPROM to CPU is good, because it looks like the
> CPU is executing the instructions correctly.
>
> But look at the 1210 first! (see my earlier reply).
>
> --John
>
>

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Max Scane
2013-10-01 10:56:41 UTC
Permalink
Well first of all, congratulations!

It is always a great feeling when your board comes to life.

I have to admit though that I didn't know that the DS1210 needed to have a
battery connected for it to work!!

I have several SBCs a couple of N8s and a couple of Zetas (which do have
batteries) and I haven't noticed this issue.

I will look closer into this for sure.

Cheers!

Max




On Tue, Oct 1, 2013 at 8:42 PM, opticpow <wayne-***@public.gmane.org> wrote:

> Ok, WOW...um WOW.
>
> First Wow cause I now have a working board. Second Wow for how something
> so simple has been critical to getting a working board.
>
> This issue was the DS1210. I have pulled it as jumpered as per John's
> message and that solved the problem. A BIG thanks to Oscar, John, Max &
> Doug for all the help.
>
> I have two questions:
>
> 1. Did I miss some instruction somewhere that describes how the battery &
> DS1210 works? How did everyone else not have the same issue???
> 2. I'm still a little lost as to what jumpers / inputs I need to ground
> when the DS1210 is in circuit? I'm aware of JP1. Is BT1 related?
>
> Thanks,
>
> Wayne.
>
>
> On Tuesday, October 1, 2013 10:47:33 AM UTC+10, John Coffman wrote:
>>
>> Wayne,
>>
>> What a puzzle.
>>
>> All those signals look good at the test points. Are they good at all
>> points they route to? (more buzzing traces)
>>
>> A bad RAM chip could also explain the problem. Use you logic probe to
>> check each data bit to see if the correct value is going to RAM and coming
>> back correctly to the Z80.
>>
>> I'd say the data path from EPROM to CPU is good, because it looks like
>> the CPU is executing the instructions correctly.
>>
>> But look at the 1210 first! (see my earlier reply).
>>
>> --John
>>
>> --
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Douglas Goodall
2013-10-01 10:57:08 UTC
Permalink
Wayne, great to hear things are working. Part of the N8VEM experience seems to be
getting down and dirty with the signals and learning how things really work. That is
how you end up feeling confident you can make it work, no matter how deep you have
to dig.

Because you were willing to ask for help, other on the list now are reminded of this
aspect of the DS1210 and may not have to suffer as much. You are also certainly
welcome to write up your experience and post it in the wiki where other builders
can find it later.

Each of my successful N8VEM projects have resulted from some help from others.
Since we share the experience of building these boards, we have a common ground,
so to speak with others. And of course there is the big thrill when it starts working. :-)

Take pictures, post them on the list or on the wiki. Have fun.

Douglas


On Oct 1, 2013, at 3:42 AM, opticpow <wayne-***@public.gmane.org> wrote:

> Ok, WOW...um WOW.
>
> First Wow cause I now have a working board. Second Wow for how something so simple has been critical to getting a working board.
>
> This issue was the DS1210. I have pulled it as jumpered as per John's message and that solved the problem. A BIG thanks to Oscar, John, Max & Doug for all the help.
>
> I have two questions:
>
> 1. Did I miss some instruction somewhere that describes how the battery & DS1210 works? How did everyone else not have the same issue???
> 2. I'm still a little lost as to what jumpers / inputs I need to ground when the DS1210 is in circuit? I'm aware of JP1. Is BT1 related?
>
> Thanks,
>
> Wayne.
>
> On Tuesday, October 1, 2013 10:47:33 AM UTC+10, John Coffman wrote:
> Wayne,
>
> What a puzzle.
>
> All those signals look good at the test points. Are they good at all points they route to? (more buzzing traces)
>
> A bad RAM chip could also explain the problem. Use you logic probe to check each data bit to see if the correct value is going to RAM and coming back correctly to the Z80.
>
> I'd say the data path from EPROM to CPU is good, because it looks like the CPU is executing the instructions correctly.
>
> But look at the 1210 first! (see my earlier reply).
>
> --John
>
>
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---
Douglas Goodall
doug-***@public.gmane.org
http://goodall.us.com
WQRLl515

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opticpow
2013-10-01 11:09:09 UTC
Permalink
Hi Doug, I have certainly enjoyed and benefited from the debugging I have
done. In fact I'm thinking about documenting the debugging I've have done.

I'm just curious how I've seemingly missed something minor for so long!!

Wayne

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John Coffman
2013-10-01 13:02:51 UTC
Permalink
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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On 10/01/2013 04:09 AM, opticpow wrote:
<blockquote
cite="mid:17ff4891-21a4-4b42-95fe-5338fc1dbe2e-/***@public.gmane.org"
type="cite">
<div dir="ltr"><br>
Hi Doug, I have certainly enjoyed and benefited from the
debugging I have done. In fact I'm thinking about documenting
the debugging I've have done. <br>
<br>
I'm just curious how I've seemingly missed something minor for
so long!!<br>
</div>
</blockquote>
<br>
Observation:<br>
<br>
SBC v1 did not have the DS1210 battery backup, so this was never an
issue.<br>
<br>
AFAIK, no s/w uses the memory retention feature of the SBC v2.&nbsp; BUT,
all BIOS's use the 1302 SRAM.&nbsp; So most builders probably had a
battery connected from the start.<br>
<br>
--John<br>
<br>
[Memory retention IS an issue with the 4MEM board, since it is so
often used as a Ramdisk on the SBC-188.&nbsp; The battery jumpers are set
to use either VBAT1 or VBAT2 <u>or both</u>, with easy grounding of
either one if not in use.]<br>
<br>
</body>
</html>

<p></p>

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p***@public.gmane.org
2013-10-01 18:58:14 UTC
Permalink
Hi gang,

First, glad that Wayne has his board fixed.
Second, I recently completed my 1st N8VEM board, and I decided to bypass the DS1210 chip. Why? My personal understanding is that if a filesystem write sequence is interrupted by a board power-down, then there's a chance that I'll have inconsistent backed-RAM storage. There are SW measures to overcome such issues, but I don't have any knowledge of whether CPM supports transactional writes to its filesystems.

I would be glad if someone shares his point of view about the DS1210 advantages.

Kind regards,
picmaster


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John Coffman
2013-10-01 12:50:47 UTC
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<br>
<br>
On 10/01/2013 03:42 AM, opticpow wrote:
<blockquote
cite="mid:d535ddd1-2662-4b6b-9b15-b86816a19901-/***@public.gmane.org"
type="cite">1. Did I miss some instruction somewhere that
describes how the battery &amp; DS1210 works? How did everyone
else not have the same issue???<br>
</blockquote>
<br>
<blockquote
cite="mid:d535ddd1-2662-4b6b-9b15-b86816a19901-/***@public.gmane.org"
type="cite">2. I'm still a little lost as to what jumpers / inputs
I need to ground when the DS1210 is in circuit? I'm aware of JP1.
Is BT1 related?<br>
</blockquote>
<br>
I had to look at the schematic to refresh my memory.&nbsp; The DS1210 has
two battery inputs.&nbsp; VBAT2 is connected to ground, so it is never a
problem.&nbsp; VBAT1 is connected to the battery input of the DS1302
also, so it is powering two devices.&nbsp; Look at the clock circuit for
the battery connections.&nbsp; You have two choices:&nbsp; the backplane (JP1)
or battery connector (BT1, next to the LED) are in parallel.&nbsp; You
really need to power the DS1302, so with no backplane, you'll need a
battery connected to BT1.&nbsp; Watch out to get the polarity correct!&nbsp;
With the DS1210 installed do either:<br>
<br>
&nbsp;&nbsp;&nbsp; 1.&nbsp; Connect BT1 and leave JP1 open (unless you want to power the
backplane battery line)<br>
&nbsp;&nbsp;&nbsp; 2.&nbsp; Leave BT1 open; short JP1, and connect a battery to the
backplane.<br>
&nbsp;&nbsp;&nbsp; 3.&nbsp; Leave JP1 open; short BT1, and have no battery backup for
1210 or 1302.<br>
<br>
Running with the DS1210 out of the circuit and pins 1-8, 5-6 shorted
is highly satisfactory.<br>
<br>
Thanks to Oscar for nailing this one.<br>
<br>
--John<br>
<br>
<br>
</body>
</html>

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John Coffman
2013-09-26 18:16:37 UTC
Permalink
opticpow
2013-09-28 05:50:26 UTC
Permalink
Hi John, thanks for the detailed info. I'm away for the weekend so I'm hold for a few days.

Cheers

Wayne
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