[N8VEM: 17860] Re: Vintage + modern = fun

[Nikolay Dimitrov]

Hi Grant,

I was looking at this code:

-- Serial clock DDS
-- 50MHz master input clock:
-- Baud Increment
-- 115200 2416
-- 38400 805
-- 19200 403
-- 9600 201
-- 4800 101
-- 2400 50
serialClkCount <= serialClkCount + 2416;

Because of the 1-bit DDS, the actual frequency of serialClkCount should
jump between 50e6/27 and 50e6/28 (the DDS works as fractional divider).
This jumping creates phase noise, which can lead to somewhat unstable
work with some serial ports. If we just divide the system clock (50MHz)
by 27, we get a frequency which is +0.46% within the expected even for
115200, but with a nice clean clock.
Another option is to use the on-chip digital frequency synthesizer
(Xilinx have it inside their DCM, Digital Clock Manager, but I'm not
sure how's that for Altera). What do you think about this?

Kind regards,
Nikolay

[Grant Searle]

Jitter is not an issue - it is very minor, and each clock is only 1/16th of
the total so the jitter percentage is tiny compared to the bit length.
DDS allows a very fine clock speed adjustment (at the expense of jitter). I
tried both but find the simple DDS approach preferable.

Regards.

Grant

Post by Nikolay Dimitrov
Hi Grant,
-- Serial clock DDS
-- Baud Increment
-- 115200 2416
-- 38400 805
-- 19200 403
-- 9600 201
-- 4800 101
-- 2400 50
serialClkCount <= serialClkCount + 2416;
Because of the 1-bit DDS, the actual frequency of serialClkCount should
jump between 50e6/27 and 50e6/28 (the DDS works as fractional divider).
This jumping creates phase noise, which can lead to somewhat unstable work
with some serial ports. If we just divide the system clock (50MHz) by 27,
we get a frequency which is +0.46% within the expected even for 115200, but
with a nice clean clock.
Another option is to use the on-chip digital frequency synth...