[N8VEM: 20062] M68EC0x0IDP bus timing, looking for lost documentation

[Carlo Pisani]

hi guys
I got a vintage (1992..1997) development board, it comes with a pretty
68000 CPU, ram, serials, timers, everything is fine, the IDP-board was
designed to provide a flexible, expandible platform for CPU evalutation,
software development, and hardware development support. The basic
functionality of the IDP can be supplement with a variety of standard
IDP-bus products as well as customer defineded modules, so ... this board
has a custom bus, handled by an fpga, I have no detailed documentation
about, while I know, from the included paper, that up to 5 expansion
modules are allowed, and *MC688916 (PLL)* clock synchronizer must be
present on each I/O module to synchronize clocks to the bus clock (with
3nsec of clock skew).

The *Slot Decoding* goes easy because each I/O slot has its own slot enable
signal generated by the FPGA on IDP motherboard. Each /SLOT is based on
A27..A24, which reduces the address decoding overhead for the I/O module.
The slot size is 16MB, so the slots are located at $0(n)0xx xxxx. Good!

I have already written a minimal BSP to take the control, everything is
fine, but this board has no flash and no lan, so I'd like to develop an
hardware module in order to attach 8Mbyte of NVRAM, plus a CS8900 ethernet.

In order to achieve this purpose, I need to develop a fsm with a little 5V
tolerant CPLD (it handles the bus-slot), but about the *IDP Bus Timing* I
have absolutely no documentation. What I have is a little blue card in
where I can read the following:

Quote

Bus Timing

For information on M68EC0x0IDP bus timing, write the following address:

Motorola
High-Performance MPU Division
ATTN: IDP Technical Support
Mail Stop OE-33
6501 William Cannon Drive West
Austin, Texas 78735-8598 USA


I have already tried to contact the *DNA division* and they have told me
that board is too obsolete for them, so they have no documentation.

does anyone know ? did anyone played with these boards ?

thanks
Carlo