[N8VEM: 19989] ECB MC68030 Status

[John Coffman]

Version 1.0 board: extra decoupling, as reflected in the updated parts
list, and extra decoupling on the backplane stabilizes the DRAM memory
operations. However, 16Mhz seems to be the highest CPU clock rate
achievable.

Interestingly, the electrolytic caps appear to require a weeklong
burn-in in order to fully form. This burn-in period has been required
on both of the boards that I have built up.

I have a 64Mb SIMM under test now, requiring only the installation of
the 16mb/64mb jumper. It is performing the memory TEST3.BIN as well as
the 16Mb modules. Double sided SIMMs of that size are next to test, but
I do not have parts in hand yet.

Coming update:
As soon as I have the parts, I will be testing a board update to replace
the 64Mhz oscillator and one of the 74F195's. The previously
distributed schematic of a test of a reconfigured 74F195 is now
discarded. If you are at the stage of acquiring parts, consider getting
an extra 74F74 (D-flop), and a 74F112 (J-K flop). I would prefer to use
the 74F114 (J-K flop), but it is very hard to find. The '112 is a
larger package, but is much more available.

If this update works as I think it should, the board speed may likely be
increased to 20-25Mhz.

[It is possible the trial will not work; but the only exposure is the
cost of 2 parts, with a much larger saving in shipping charges.]

--John

[John Coffman]

The previous post led to a much simpler trial update, which has worked out
very well.

ALL BOARDS SHOULD BE UPDATED TO VERSION 1.1, by adding a single wire, and
updating one GAL. Details of the update, including a photo of the added
wire, are documented on the Wiki.

Page: http://n8vem-sbc.pbworks.com/w/page/97436211/KISS%2068030
Pix:
Loading Image...
Notice:
http://n8vem-sbc.pbworks.com/w/file/99196078/Update-KISS-version_1.0_to_1.1.pdf
PLD:
http://n8vem-sbc.pbworks.com/w/file/99196090/KISS68030-PLD-20150815.zip

Board operation at 25Mhz is error-free (DRAM overnight testing with
TEST3.BIN).

--John

Post by John Coffman
Version 1.0 board: extra decoupling, as reflected in the updated parts
list, and extra decoupling on the backplane stabilizes the DRAM memory
operations. However, 16Mhz seems to be the highest CPU clock rate
achievable.
Interestingly, the electrolytic caps appear to require a weeklong
burn-in in order to fully form. This burn-in period has been required
on both of the boards that I have built up.
I have a 64Mb SIMM under test now, requiring only the installation of
the 16mb/64mb jumper. It is performing the memory TEST3.BIN as well as
the 16Mb modules. Double sided SIMMs of that size are next to test, but
I do not have parts in hand yet.
As soon as I have the parts, I will be testing a board update to replace
the 64Mhz oscillator and one of the 74F195's. The previously
distributed schematic of a test of a reconfigured 74F195 is now
discarded. If you are at the stage of acquiring parts, consider getting
an extra 74F74 (D-flop), and a 74F112 (J-K flop). I would prefer to use
the 74F114 (J-K flop), but it is very hard to find. The '112 is a
larger package, but is much more available.
If this update works as I think it should, the board speed may likely be
increased to 20-25Mhz.
[It is possible the trial will not work; but the only exposure is the
cost of 2 parts, with a much larger saving in shipping charges.]
--John