John Coffman
2015-10-14 15:41:14 UTC
All,
In the hopes of reproducing the memory failures with TEST3.BIN I have
finally received 74F257 chips to replace my 74F257A chips. Both of the
boards I built up use vanilla 74F195 chips.
Tests done on my first board: 25Mhz CPU osc., 64Mhz DRAM osc. 2 dual
sided 32Mb off-brand 60ns memory SIMMs.
Original memory chip set: Signetics 74F195N, 3 x Motorola MC74F257A
-- no errors
Last night's test: same Signetics 74F195N, 3 x Fairchild 74F257PC --
ran TEST3 all night with no errors (330 passes)
I had hoped to show that by reducing the DRAM oscillator frequency to
50Mhz, the memory errors would cease. I am unable to introduce memory
errors by going to vanilla 257 chips, which are slower than the 257A chips.
The 22V10 GALs use in the DRAM memory access circuitry are USED Lattice
-7 ns parts, reprogrammed.
Would others kindly contribute their comments on how the memory error
problems were solved. My own way was more electrolytic decoupling, and
a week-long burn-in.
--John
In the hopes of reproducing the memory failures with TEST3.BIN I have
finally received 74F257 chips to replace my 74F257A chips. Both of the
boards I built up use vanilla 74F195 chips.
Tests done on my first board: 25Mhz CPU osc., 64Mhz DRAM osc. 2 dual
sided 32Mb off-brand 60ns memory SIMMs.
Original memory chip set: Signetics 74F195N, 3 x Motorola MC74F257A
-- no errors
Last night's test: same Signetics 74F195N, 3 x Fairchild 74F257PC --
ran TEST3 all night with no errors (330 passes)
I had hoped to show that by reducing the DRAM oscillator frequency to
50Mhz, the memory errors would cease. I am unable to introduce memory
errors by going to vanilla 257 chips, which are slower than the 257A chips.
The 22V10 GALs use in the DRAM memory access circuitry are USED Lattice
-7 ns parts, reprogrammed.
Would others kindly contribute their comments on how the memory error
problems were solved. My own way was more electrolytic decoupling, and
a week-long burn-in.
--John
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