[N8VEM: 17113] PropIO: nCS-to-nWAIT delay improvement

[kuroneko]

The current s/w solution offers a 7 cycle delay (prop system clocks)
between nWAIT going active after nCS goes low. This has been considered too
long for certain use cases. I'll attach a proof of concept file which gets
this delay down to 3 cycles. What it boils down to is the use of the write
modifier on *waitpeq*:

' Wait for nCS to go active and perform outa += msk2 which makes
' outa := 2*outa + msk1 meaning now nWAIT is active.

loop_dira andn dira, #$FF ' data bus input
loop_outa mov outa, msk0 ' nWAIT inactive
loop waitpeq outa, msk2 wr

HTH,
Marko

[Wayne Warthen]

Hi Marko,

This looks great! It should significantly improve the performance limits
of the current PropIO. I will try this in the current firmware and report
back. I probably won't get to this for a few days though.

Thanks,

Wayne

Post by kuroneko
The current s/w solution offers a 7 cycle delay (prop system clocks)
between nWAIT going active after nCS goes low. This has been considered too
long for certain use cases. I'll attach a proof of concept file which gets
this delay down to 3 cycles. What it boils down to is the use of the write
' Wait for nCS to go active and perform outa += msk2 which makes
' outa := 2*outa + msk1 meaning now nWAIT is active.
loop_dira andn dira, #$FF ' data bus input
loop_outa mov outa, msk0 ' nWAIT inactive
loop waitpeq outa, msk2 wr
HTH,
Marko

[Wayne Warthen]

Hi Marko,

Found the time to try your performance improvement. It definitely helped
and I was able to run my SBC V2 at 8MHz with PropIO. Previously, the
fastest I could achieve was 6MHz. I had hoped it might be able to go even
faster, but I was not successful at 10MHz.

I am attaching the code module with the change in case you want to take a
look. I think I did this as you indicated, but probably worth having you
double check me. Look around line 340.

I will soon release a minor revision of RomWBW that includes this updated
firmware image for the PropIO.

I am also back on track toward getting a V2 of PropIO produced which should
take care of the speed issue completely.

Thanks,

Wayne

Post by kuroneko
The current s/w solution offers a 7 cycle delay (prop system clocks)
between nWAIT going active after nCS goes low. This has been considered too
long for certain use cases. I'll attach a proof of concept file which gets
this delay down to 3 cycles. What it boils down to is the use of the write
' Wait for nCS to go active and perform outa += msk2 which makes
' outa := 2*outa + msk1 meaning now nWAIT is active.
loop_dira andn dira, #$FF ' data bus input
loop_outa mov outa, msk0 ' nWAIT inactive
loop waitpeq outa, msk2 wr
HTH,
Marko

[kuroneko]

Post by Wayne Warthen
Found the time to try your performance improvement. It definitely helped
and I was able to run my SBC V2 at 8MHz with PropIO. Previously, the
fastest I could achieve was 6MHz. I had hoped it might be able to go even
faster, but I was not successful at 10MHz.

I had expected slightly more but figured that the prop delay is only one
part of the equation here. Purely out of curiosity, is there any chance of
getting a scope image containing SBC clock, nCS (at prop pin) and nWAIT (at
prop pin and real)? Doesn't matter if it's with 7 or 3 cycle delay.

Thanks,
Marko

[Wayne Warthen]

Hi Marko,

I don't have a scope, but could hook up my logic analyzer as requested. I
think that would get you the the information you want.

You will need to give me a few days to get to this though. Too many irons
in the fire at the moment.

Thanks,

Wayne

Post by Wayne Warthen
Found the time to try your performance improvement. It definitely helped

Post by Wayne Warthen
and I was able to run my SBC V2 at 8MHz with PropIO. Previously, the
fastest I could achieve was 6MHz. I had hoped it might be able to go even
faster, but I was not successful at 10MHz.

I had expected slightly more but figured that the prop delay is only one
part of the equation here. Purely out of curiosity, is there any chance of
getting a scope image containing SBC clock, nCS (at prop pin) and nWAIT (at
prop pin and real)? Doesn't matter if it's with 7 or 3 cycle delay.
Thanks,
Marko

[kuroneko]

Appreciated, whenever it's convenient.