Hi Wolfgang,
I recognise the font of the PIN DESCRIPTIONS document you attached, I have
that Zilog Data Book sitting right behind me in my office!
I agree we need to work out the Power On status. The propeller boots up
with all pins HiZ, but it can be programmed to poll repeatedly the port
request, transfer data and then release the Z80. It is possible to program
the propeller to always release the /wait line after a short delay, so
there is no problem with the Z80 crashing.
Ok, bouncing on the HC125. I agree that could be a problem. 74LS06 is
good, but it inverts. There are several 'open collector' chips
(01,05,06,07,09,38) ref http://www.futurlec.com/IC74LS00Series.shtml
To decode the I/O port, a LS688 is a generic solution that can be set to
read any port with 8 jumpers. The output is LOW, so we need a non
inverting gate. So use the LS07 instead of the LS06.
Will this work at 10Mhz? If the appropriate port is decoded, the absolute
maximum delay for the LS688 is 30ns
(http://www.futurlec.com/74LS/74LS688.shtml) and the maximum delay for the
LS07 is another 30ns. So max 60ns and typical delay is more like max 32ns.
So this should be fast enough.
Do you see any problems with the attached schematic?
Cheers, James Moxham
On Thu, 09 Jan 2014 04:29:26 +1030, Wolfgang Kabatzke
Post by Wolfgang KabatzkeHi James,
"yes".
A FF has two states and itŽs not sure after Power-On that an FF is in
the "right state". It could be in state 1 or in state 2. I "learned"
this >ws I worked as hardware developer. So You need in each case if You
use a FF to control states, RAM etc, an input from /RESET to >guarantee
that the FF is after Power ON in the right state. So it could be that
the computer is after Power On complete blocked by WAIT >from the
WAIT-Logic.
74X125 is nit the good and right solution. Each transition from L/H to
L/Hi is combined with bouncings/debouncings on the signal line.
Normally is on each ECB-CPU the /WAIT-line direct connected to the
Z80-WAIT-Pin. If there is trouble on the line the Z80 may be come >into
confued situations. Ok, in SBC-V2 the WAIt-line is driven by 74x244, but
this is not normal because we have additional delays and >we need
additional resistor(s) on the ECB-Bus because WAIT is Wired-(N)OR.
I use each time 74x06 or 74x03 . And in the CPU-Spec is written "Input,
active low", not "input, active low, 3-state".
I see that I must look for another solution. My idea was the improving
of my ECB-System to minimum 10MHz. PropIO is the "handbrake >for my
Z80-Mercedes / Porsche" and I donŽt like this way. So I ordered the
8563-IC + 82C42 and IŽm switching to Colour-VDU.
A solution could be to leave the polling modus when we use ProIO and use
the Interrupt. So we have an plus in speed because we have >only WAIT if
there is an reals communication between Z80 and PropIO.
What Do You think?
Best regards
Wolfgang
Well this has me thinking - what is the *simplest* wait state circuit?
Ok, one circuit we have uses a '74 latch. Why is there a latch? Well it
is to trap an /IORQ to a particular port and then >>make /WAIT low
until it is reset by another circuit. The latch is there to make sure
it traps the Z80 in a wait state no >>matter what the speed is.
But - what happens next? How does the slave circuit know that the Z80
is in a wait state? Well, because the decoded port >>address has gone
low.
Now, if the slave is reading the decoded port as being low, the Z80
must have been trapped in a wait state as soon as the >>port was
addressed. If it had clocked a few more clocks, the port address would
no longer be valid nor would the data >>bus.
So, I am thinking that you do not need a latch. All you need is an OR
gate. The decoded address is one input to the OR >>gate, the slave
clear is the other input, and the output goes to /WAIT. In normal
operation the slave input to the OR gate >>is low. As soon as the port
is addressed, /WAIT goes low and the Z80 goes into a WAIT state. The
Z80 becomes the >>latch.
If this logic is correct, then the next thing to consider is that the
ECB bus /WAIT pin is not the same as the Z80 pin and >>has the states
LOW and HiZ, rather than LOW and HIGH. So you need a 7406. But then we
need two chips - '32 and '06. >>How about a 74LS125. Connect the enable
to the input and it changes L/H to L/HiZ. And looking at the logic, I
think you >>can use another 125 as an OR gate. Connect one input to the
A input, the other input to the C input, and have a 10k >>pullup on the
output. The only time the output is low is if both inputs are low.
Maybe I'm missing something, but I think it can be done with one '125
chip, using two gates.
Am I missing something?
Cheers, James Moxham
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