[N8VEM: 16909] External memory

[James Moxham (Dr_Acula)]

Is it possible to add external memory with an ECB board?

I see there is a 4meg board but this appears to be for the 188, ? not for
the SBC-V2.

Thinking of just a simple addition of one extra 512mb sram chip, how would
this interface with the SBC-V2? I see there are banks of 32k and dividing a
512k chip into 32 banks, there are 16 of these. Numbering these from 0 to
15 with 0 at the bottom, I think what happens is that if A15 is high, then
bank 15 is always selected. If A15 is low, then one of 16 banks gets
selected as the low bank.

Is there a design that would integrate with this to add another 512k ram
chip eg in some way where A15 being high still selects the top bank of the
first ram chip, but now there are 32 banks of 32k that can be selected for
the low bank.

The bit that has me confused is how to do this on a separate board running
off the ECB bus. I think to do this, somehow if A15 is low, there needs to
be some way of completely deselecting the ram chip on the SBC-V2 so that
the ram chip(s) on an external board don't conflict on the data bus.

And perhaps a related question, this might require sending data to a latch
on an external board, and if so, this latch would need a port number. Is
there some list on the N8VEM of port numbers and is there some sort of
protocol to assigning new port numbers?

Many thanks in advance.

James Moxham
Adelaide, Australia

[John Coffman]

James,

There is no way to add extra memory to the ECB running the SBC v2.

You are correct that the 4MEM board is for use with the SBC-188; but it
can also be used with the Mini-M68K and the Z180 Mark IV.

Part of the problem adding extra memory has to do with the number of
address bits:
SBC v2 16 external address bits
SBC-188 20 bits
Mini-M68K 24 bits (24 bits driven, actually only 22 really used)
Mark IV 24 bits

4MEM 20 bit address selection

In use with the SBC-188, the 4MEM board fills out the address space
beyond 512K. Above 640K, it may be used to provide Expanded Memory
(i.e., up to 4meg mapped in 16K pages into a 64K window).

In use with the Mini-M68K, which has 2048K memory on-board, the 4MEM
board can address a 1meg area from 2-3megs, mapping 16K pages into the
1Meg region. So it may be used to expand the Mini-M68K from 2meg to 3meg.

The Z180 Mark IV is set up to use external memory, mapping either ROM or
external RAM into the low 32K window. The high 32K always maps to the
512K on-board RAM. With a 4MEM board, the low 32K window may be mapped
to on-board RAM, on-board ROM up to 1Meg, or off-board memory from 1meg
to 16meg. The 4MEM board uses only 20 bit addressing, so it will map
into all 1Meg regions above the first, the external memory region.

A future memory board for the ECB bus which uses 24-bit addressing,
would be usable with the Mini-M68K to add 1.5Meg of RAM, or would be
usable with the Z180 Mark IV to add 15Meg of RAM (from 1meg to 16meg)
using the Mark IV mapping hardware.

--John

Post by James Moxham (Dr_Acula)
Is it possible to add external memory with an ECB board?
I see there is a 4meg board but this appears to be for the 188, ? not
for the SBC-V2.
Thinking of just a simple addition of one extra 512mb sram chip, how
would this interface with the SBC-V2? I see there are banks of 32k and
dividing a 512k chip into 32 banks, there are 16 of these. Numbering
these from 0 to 15 with 0 at the bottom, I think what happens is that
if A15 is high, then bank 15 is always selected. If A15 is low, then
one of 16 banks gets selected as the low bank.
Is there a design that would integrate with this to add another 512k
ram chip eg in some way where A15 being high still selects the top
bank of the first ram chip, but now there are 32 banks of 32k that can
be selected for the low bank.
The bit that has me confused is how to do this on a separate board
running off the ECB bus. I think to do this, somehow if A15 is low,
there needs to be some way of completely deselecting the ram chip on
the SBC-V2 so that the ram chip(s) on an external board don't conflict
on the data bus.
And perhaps a related question, this might require sending data to a
latch on an external board, and if so, this latch would need a port
number. Is there some list on the N8VEM of port numbers and is there
some sort of protocol to assigning new port numbers?
Many thanks in advance.
James Moxham
Adelaide, Australia
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[James Moxham]

Thanks John for the very helpful reply.

Ok, your comments below are exactly what I want - but with a Z80!

Maybe it needs a new board, but I'm designing one at the moment and I
think it might be possible with a Z80 chip.

I don't have an onboard rom so the ram decode ends up simpler - 4 bits on
a latch and an HC32 chip.

Only 4 bits of the 174 latch are being used and there are 6 bits. So let's
add another bit and we can call this bit "external ram select". If it is
low, everything is decoded as per normal. If it is high, then if A15 is
low, then the onboard ram chip /CS line is pulled high and the onboard ram
is not selected. I think that is possible with some AND OR and inverters
and I have several spare gates for these.

Normally, deselecting the ram chip while running a program would cause the
Z80 to crash. But you would only be setting this latch bit from software
if you had an external ram board. On the external ram board, we should be
able to detect all that has happened on the main board, even to the point
of mirroring the latch, and then if external ram is selected, we serve up
the appropriate 32k block.

Once it is working on one ram chip, adding more chips should be fairly
simple.

So I think this might be possible with just a few extra logic gates on the
main board. Is there a catch?

Cheers, James




PS - where I am heading with this is building a touchscreen board, and for
those one needs to move large blocks of memory. eg 240x320 with 2
bytes/pixel = 153600 bytes for one screen, about 32k to 50k for a font
library etc. I have this working on a propeller design playing pacman and
moving sprites around quickly and I think it should be possible with a Z80
driving it instead of the propeller. So I need lots of external ram. The
Z80 block move instructions will be perfect for moving data.

Post by John Coffman
The Z180 Mark IV is set up to use external memory, mapping either ROM or
external RAM into the low 32K window. The high 32K always maps to the
512K on-board RAM. With a 4MEM board, the low 32K window may be mapped
to on-board RAM, on-board ROM up to 1Meg, or off-board memory from 1meg
to 16meg. The 4MEM board uses only 20 bit addressing, so it will map
into all 1Meg regions above the first, the external memory region.

--

[John Coffman]

James,

You might take a look at the Mark IV external addressing.

Keep in mind that the Z180 MMU uses 4K pages in a 64K address space.
Then the Z180 external addressing uses 20-bits.

Page 9 of the schematic displays the 2 x 512K pages of on-board
ROM/RAM. Then U31 comes into play, allowing the ROM to be paged as two
512K pages into low 20-bit memory; and then beyond 1M U31 contains the
external address bits to put out on the extended ECB bus. The XMEM and
/XMEM signals come into play on the BusDrivers.sch sheet, p5.

I attach the schematic.

--John

Post by James Moxham
Thanks John for the very helpful reply.
Ok, your comments below are exactly what I want - but with a Z80!
Maybe it needs a new board, but I'm designing one at the moment and I
think it might be possible with a Z80 chip.
I don't have an onboard rom so the ram decode ends up simpler - 4 bits
on a latch and an HC32 chip.
Only 4 bits of the 174 latch are being used and there are 6 bits. So
let's add another bit and we can call this bit "external ram select".
If it is low, everything is decoded as per normal. If it is high, then
if A15 is low, then the onboard ram chip /CS line is pulled high and
the onboard ram is not selected. I think that is possible with some
AND OR and inverters and I have several spare gates for these.
Normally, deselecting the ram chip while running a program would cause
the Z80 to crash. But you would only be setting this latch bit from
software if you had an external ram board. On the external ram board,
we should be able to detect all that has happened on the main board,
even to the point of mirroring the latch, and then if external ram is
selected, we serve up the appropriate 32k block.
Once it is working on one ram chip, adding more chips should be fairly
simple.
So I think this might be possible with just a few extra logic gates on
the main board. Is there a catch?
Cheers, James
PS - where I am heading with this is building a touchscreen board, and
for those one needs to move large blocks of memory. eg 240x320 with 2
bytes/pixel = 153600 bytes for one screen, about 32k to 50k for a font
library etc. I have this working on a propeller design playing pacman
and moving sprites around quickly and I think it should be possible
with a Z80 driving it instead of the propeller. So I need lots of
external ram. The Z80 block move instructions will be perfect for
moving data.

Post by John Coffman
The Z180 Mark IV is set up to use external memory, mapping either ROM or
external RAM into the low 32K window. The high 32K always maps to the
512K on-board RAM. With a 4MEM board, the low 32K window may be mapped
to on-board RAM, on-board ROM up to 1Meg, or off-board memory from 1meg
to 16meg. The 4MEM board uses only 20 bit addressing, so it will map
into all 1Meg regions above the first, the external memory region.

--

[p***@public.gmane.org]

Hi James,

Sorry for asking this, but I'm catching up with my e-mails - the idea of your
schematic is to implement a bootstrap mechanism for the Z80, is this correct?
If so, looks nice, I also had similar ideas before some months, but was too
lazy to implement them (although I intended to use a PIC mcu in order to use
only 1 IC).

I like that you preserved the "top page addressing" logic of the original SBC
V2 (IC16A/B/C/D), which imho is one of the most logic-efficient ways to implement
a paging logic.

I have 2 questions to you:

1.How do you actually intend to bootstrap the Z80? As far as I remember, it's
done either by toggling the CLK pin in slow-speed by the bootstrap circuit and
decoding addresses/providing data on the CPU data bus, or the CPU CLK is at
high-speed clock (2-5-10 MHz), and the bootstrap manages the WAIT signal, and
again decodes addresses/provides data. In both cases your bootstrap circuit
will need non-zero time to react - I'm not sure how fast is the PROP, but working
through an IO-extender will be definitely slow.

2. How do you sense that the bootstrap process is completed and then disconnect
the IO-extenders + PROP from the CPU bus?

Regards,
picmaster

PS: Boy, this MCP23017 looks like a modern I2C-based 8255, nice!

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[p***@public.gmane.org]

Looking again at this question, I suppose that the bootstrap circuit works by
resetting the Z80, programming the SRAM, 3-stating the IO-expander pins and
then starting the Z80. This looks like a simpler solution than what I described
before.

Regards,
picmaster

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[James Moxham (Dr_Acula)]

@picmaster, yes that is correct - hold the Z80 in reset, put a boostrap
program in ram, then let the Z80 run.

@John, thanks for the schematic. Very helpful.

Attached is a schematic of the external ram idea. Normally the 174 latch
resets and starts up low, so EXT_RAM is always low and the MREQ signal
passes through as normal. If A15 is high, then this overrides any external
ram, and always reads from the local ram chip. So the condition to test for
is if EXT_RAM is high and if A15 is low. Then the local ram chip is
deselected. On an external ram board this logic can be replicated and any
32k block from any number of ram chips can then be selected. I hope the
logic is correct!

[John Coffman]

James,

The select may be okay, but there is another factor to consider: the
data direction of the LS245 which passes D0..D7 in and out of the CPU
board. You will also have to change this logic to account for the
selection of external RAM. When on-board RAM is selected, DATA_DIR must
say "out/out." When external RAM is selected, DATA_DIR must say
"in/out" during R/W. During DMA to on-board RAM, DATA_DIR must say
"out/in" during R/W. And during DMA to external RAM, DATA_DIR must say
"in/in."

Andrew's DATA_DIR circuit is amazing for its simplicity. I can't
understand it; but make a truth table and you will see that it gets the
DATA_DIR correct all the time. Although there are currently no external
boards that do DMA to/from memory, a circuit that gets it right
depending upon whether on-board or external memory is accessed, is quite
a trick.

--John

Post by James Moxham (Dr_Acula)
@picmaster, yes that is correct - hold the Z80 in reset, put a
boostrap program in ram, then let the Z80 run.
@John, thanks for the schematic. Very helpful.
Attached is a schematic of the external ram idea. Normally the 174
latch resets and starts up low, so EXT_RAM is always low and the MREQ
signal passes through as normal. If A15 is high, then this overrides
any external ram, and always reads from the local ram chip. So the
condition to test for is if EXT_RAM is high and if A15 is low. Then
the local ram chip is deselected. On an external ram board this logic
can be replicated and any 32k block from any number of ram chips can
then be selected. I hope the logic is correct!
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[James Moxham]

Hmm, good points, that does make it more complicated. I might have to
leave this idea for the moment, I think I am going to run out of spare
gates.

I'll have a think about this some more.

Cheers, James

Post by John Coffman
James,
The select may be okay, but there is another factor to consider: the
data direction of the LS245 which passes D0..D7 in and out of the CPU
board. You will also have to change this logic to account for the
selection of external RAM. When on-board RAM is selected, DATA_DIR must
say "out/out." When external RAM is selected, DATA_DIR must say
"in/out" during R/W. During DMA to on-board RAM, DATA_DIR must say
"out/in" during R/W. And during DMA to external RAM, DATA_DIR must say
"in/in."
Andrew's DATA_DIR circuit is amazing for its simplicity. I can't
understand it; but make a truth table and you will see that it gets the
DATA_DIR correct all the time. Although there are currently no external
boards that do DMA to/from memory, a circuit that gets it right
depending upon whether on-board or external memory is accessed, is quite
a trick.
--John

Post by James Moxham (Dr_Acula)
@picmaster, yes that is correct - hold the Z80 in reset, put a
boostrap program in ram, then let the Z80 run.
@John, thanks for the schematic. Very helpful.
Attached is a schematic of the external ram idea. Normally the 174
latch resets and starts up low, so EXT_RAM is always low and the MREQ
signal passes through as normal. If A15 is high, then this overrides
any external ram, and always reads from the local ram chip. So the
condition to test for is if EXT_RAM is high and if A15 is low. Then
the local ram chip is deselected. On an external ram board this logic
can be replicated and any 32k block from any number of ram chips can
then be selected. I hope the logic is correct!
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[Lars Nelson]

Thinking of just a simple addition of one extra 512mb sram chip, how would this interface with the SBC-V2?

An extra 512mb sram chip could be added to the board by soldering it on top of the existing sram except for the CS pin which needs to be wired separately. The SBC-V2 only provides 19 address lines on the board for ram addressing so another address line is needed to address 1mb of ram. The ram config latch, U12, has room for another bit and some of the spare gates could be used to generate an "A19_RAM" signal. Unfortunately there probably aren't enough spare gates remaining to also generate the chip selects for the two sram chips from /CS_RAM and A19_RAM (maybe a clever logic designer could think of a way). So modifying the board would get pretty ugly but not impossible since additional chip(s) would need to be mounted somewhere.