[N8VEM: 17227] 6502 SBC question

Discussion:

Richard Cini

2014-01-25 01:16:24 UTC

All â¹

IÂ¹m reviving an old design for a 6502 SBC that was based on Daryl RictorÂ¹s
SBC. My version has some interesting things, including a
Commodore-compatable serial interface.

Anyway, IÂ¹m adapting the old design to the new WDC chips in PLCC format and
I have a question about pull-ups on the *SO, RDY, and BE pins. In the
design, RDY, IRQ, NMI and RES are pulled-up to Vcc through a 3.3k rpack, but
the others werenÂ¹t. IÂ¹ve seen conflicting things, including the right value
for the resistors for these pins plus *IRQ and *NMI.

So, IÂ¹m looking for some advice on how to treat these pins properly. The
6502/6809 board uses 1k but not on all of those pins.

Thanks in advance!

Rich

--
Rich Cini
Collector of Classic Computers
Build Master and lead engineer, Altair32 Emulator
http://www.classiccmp.org/cini
http://www.classiccmp.org/altair32

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John Coffman

2014-01-25 20:03:04 UTC

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Rich,<br>
<br>
IRQ, NMI, RES are inputs.  The value of the pull-up resistors is
really a function of the drivers that pull the signals low, not a
function of the 6502 input.<br>
<br>
If RDY is an input, too, then it is in the same category.<br>
<br>
*SO is an output.  I imagine the choice of resistor depends upon
whether you are designing for a CMOS or NMOS 6502.  Remember, this
is an old, not very fast chip.  I am not sure what signal you are
referring to as BE, but the same considerations apply.<br>
<br>
Low resistor values give a faster rise-time on the signal, but load
the driver chips.<br>
<br>
Values in the range 1K to 47K probably work fine.  One might narrow
that range to 2K to 10K.<br>
<br>
Whenever I am in serious doubt about a pack of pull-up resistors, I
butcher a 20-pin DIP socket (machine-tooled) and socket the resistor
pack, making it easy to change -- change my mind, that is -- on a
prototype board.  I think only once in the last few years have I
decided to change the value of a pull-up SIP.<br>
<br>
--John<br>
<br>
<br>
<br>
On 01/24/2014 05:16 PM, Richard Cini wrote:
<blockquote cite="mid:CF087A98.2D9D5%25rich.cini-H+***@public.gmane.org"
type="cite">
<div>
<div>
<div>All —</div>
<div><br>
</div>
<div><span class="Apple-tab-span" style="white-space: pre;"> </span>I’m
reviving an old design for a 6502 SBC that was based on
Daryl Rictor’s SBC. My version has some interesting things,
including a Commodore-compatable serial interface.</div>
<div><br>
</div>
<div><span class="Apple-tab-span" style="white-space: pre;"> </span>Anyway,
I’m adapting the old design to the new WDC chips in PLCC
format and I have a question about pull-ups on the *SO, RDY,
and BE pins. In the design, RDY, IRQ, NMI and RES are
pulled-up to Vcc through a 3.3k rpack, but the others
weren’t. I’ve seen conflicting things, including the right
value for the resistors for these pins plus *IRQ and *NMI.</div>
<div><br>
</div>
<div><span class="Apple-tab-span" style="white-space: pre;"> </span>So,
I’m looking for some advice on how to treat these pins
properly. The 6502/6809 board uses 1k but not on all of
those pins.</div>
<div><br>
</div>
<div>Thanks in advance!</div>
<div><br>
</div>
<div>
<div>Rich</div>
<div><br>
</div>
<div>--</div>
<div>Rich Cini</div>
<div>Collector of Classic Computers</div>
<div>Build Master and lead engineer, Altair32 Emulator</div>
<div><a moz-do-not-send="true"
href="http://www.classiccmp.org/cini">http://www.classiccmp.org/cini</a></div>
<div><a moz-do-not-send="true"
href="http://www.classiccmp.org/altair32">http://www.classiccmp.org/altair32</a></div>
<div><br>
</div>
</div>
</div>
</div>
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Richard Cini

2014-01-25 20:24:20 UTC

Permalink

Thanks John. I like the idea of a swappable rpack. Pull-ups are at 3.3k
which I think should be fine.

Rich

--
Rich Cini
Collector of Classic Computers
Build Master and lead engineer, Altair32 Emulator
http://www.classiccmp.org/cini
http://www.classiccmp.org/altair32

From: John Coffman <johninsd-***@public.gmane.org>
Reply-To: N8VEM-Post <n8vem-/***@public.gmane.org>
Date: Saturday, January 25, 2014 at 3:03 PM
To: N8VEM-Post <n8vem-/***@public.gmane.org>
Subject: Re: [N8VEM: 17228] 6502 SBC question

Rich,

IRQ, NMI, RES are inputs. The value of the pull-up resistors is really a
function of the drivers that pull the signals low, not a function of the
6502 input.

If RDY is an input, too, then it is in the same category.

*SO is an output. I imagine the choice of resistor depends upon whether
you are designing for a CMOS or NMOS 6502. Remember, this is an old, not
very fast chip. I am not sure what signal you are referring to as BE, but
the same considerations apply.

Low resistor values give a faster rise-time on the signal, but load the
driver chips.

Values in the range 1K to 47K probably work fine. One might narrow that
range to 2K to 10K.

Whenever I am in serious doubt about a pack of pull-up resistors, I butcher
a 20-pin DIP socket (machine-tooled) and socket the resistor pack, making it
easy to change -- change my mind, that is -- on a prototype board. I think
only once in the last few years have I decided to change the value of a
pull-up SIP.

--John

Post by Richard Cini
All â¹
IÂ¹m reviving an old design for a 6502 SBC that was based on Daryl RictorÂ¹s
SBC. My version has some interesting things, including a Commodore-compatable
serial interface.
Anyway, IÂ¹m adapting the old design to the new WDC chips in PLCC format and I
have a question about pull-ups on the *SO, RDY, and BE pins. In the design,
RDY, IRQ, NMI and RES are pulled-up to Vcc through a 3.3k rpack, but the
others werenÂ¹t. IÂ¹ve seen conflicting things, including the right value for
the resistors for these pins plus *IRQ and *NMI.
So, IÂ¹m looking for some advice on how to treat these pins properly. The
6502/6809 board uses 1k but not on all of those pins.
Thanks in advance!
Rich
--
Rich Cini
Collector of Classic Computers
Build Master and lead engineer, Altair32 Emulator
http://www.classiccmp.org/cini
http://www.classiccmp.org/altair32
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Ian May

2014-01-29 14:56:10 UTC

Permalink

This post might be inappropriate. Click to display it.

John Coffman

2014-01-29 15:20:57 UTC

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On 01/29/2014 06:56 AM, Ian May wrote:
<blockquote
cite="mid:CAC2ufZDKAB57CoGGawGVxJX49WxBbtUx9qZTS7gfeCWfT9j8bg-JsoAwUIsXosN+***@public.gmane.org"
type="cite">
<div>
<div>
<div>John, what has been done with SO in the N8VEM and S100
designs? If it is floating difficulties with maths may
occur....<br>
</div>
</div>
</div>
</blockquote>
<br>
/SO is pulled high.  Yes, it is an input, not an output.<br>
<br>
<blockquote
cite="mid:CAC2ufZDKAB57CoGGawGVxJX49WxBbtUx9qZTS7gfeCWfT9j8bg-JsoAwUIsXosN+***@public.gmane.org"
type="cite">
<div>
<div>
<div><br>
</div>
</div>
BE is the Bus Enable pin. When it is low the address, data and
R/W pins are tri-stated. If you are not sharing the buses tie it
high. This function was not implemented on the original 6502.<br>
</div>
</blockquote>
<br>
The data sheets I have for the 65C02 do not have a BE signal.  What
pin is it on?  I have 3 pins marked NC (no connect):  5, 35, 36. 
For 6802 use in the socket, pin 35 is connected to Vcc and pin 36 is
connected to GND.  There are no option jumpers on these 3 pins.<br>
<br>
--John<br>
<br>
<br>
<br>
<br>
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Ian May

2014-01-30 13:38:05 UTC

Permalink

Hi John,
on the W65C02S DIP package pin 35 is now the only NC. Pin 36 is BE and pin
5 is MLB. I'm pretty sure pin 36 needing to be tied high has been mentioned
in the group, but I don't know if it is in the wiki. Track cutting will be
required if it is grounded. Regarding MLB - from the data sheet - "The
Memory Lock (MLB) output may be used to ensure the integrity of
Read-Modify-Write instructions in a multiprocessor system. Memory Lock
indicates the need to defer arbitration of the bus cycle when MLB is low.
Memory Lock is low during the last three cycles of ASL, DEC, INC, LSR, ROL,
ROR, TRB and TSB memory referencing instructions." The 6809E has an AVMA
which performs the same sort of function going by the data sheet
description, but I have never used it.

The W65C02 data sheet also has a specific warning about NC pins - "The No
Connect (NC) pins are not connected internally and should not be connected
externally" - I wonder why if they are not connected internally?

There is an application note here
http://www.westerndesigncenter.com/wdc/AN-002_W65C02S_Replacements.cfm"Replacement
Notes for Obsolete Versions of 6502 8-bit Microprocessors"
which identifies one more pin incompatibility. Pin 1 is now an output VPB -
Vector Pull which goes low during interrupt sequences. I don't recall that
being brought up in the group so that should be left out of the socket as
suggested for the Apple machines. Perhaps there should be a link to that
app. note in the wiki? Note that there are also recommendations for the RDY
pin: "[my comments]"

IN SUMMARY: The W65C02S6T (40 pin PDIP) is mostly pin compatible by making
the following modifications:

- 1.) Cut the trace to VPB (Pin 1). Optionally you can pull this pin up.
[Don't they mean out rather than up???]
- 2.) BE (Pin 36) should be tied directly to VDD (Pin 8).
- 3.) Add a 3.3K Ohm pull-up resistor on RDY (Pin 2) if not being
driven; Add a 3.3K Ohm series current limiting resitor to RDY (Pin 2) if
being driven.[How much does that slow it down?]
- 4.) WDC does not recommend using the SToP or WAIt instruction on the
replacement designs that do not have a current limiting resistor.

Cheers,
Ian.

Post by Ian May
John, what has been done with SO in the N8VEM and S100 designs? If it is
floating difficulties with maths may occur....
/SO is pulled high. Yes, it is an input, not an output.
BE is the Bus Enable pin. When it is low the address, data and R/W pins
are tri-stated. If you are not sharing the buses tie it high. This function
was not implemented on the original 6502.
The data sheets I have for the 65C02 do not have a BE signal. What pin is
it on? I have 3 pins marked NC (no connect): 5, 35, 36. For 6802 use in
the socket, pin 35 is connected to Vcc and pin 36 is connected to GND.
There are no option jumpers on these 3 pins.
--John
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John Coffman

2014-01-30 15:48:35 UTC

Permalink

Ian,
Rich,

The Western Digital 65c02 is a different chip from the Rockwell or
California Micro Devices 65c02's. I say this because of the different
pin out, which includes pin 5 (MLB) and pin 36 (BE). These signals are
_not_ present on the Rockwell or CMD chips.

The pins are connected to allow the 6802 or 6808 to share the same
socket on the 6x0x board. With the WD chip, two more jumpers would be
needed.

If you are going to swap processors (6502/6802) on the 6x0x board, then
the solution below will defeat the 6802. As configured, the board will
support the 65c02 from Rockwell or CMD, but not WD. If the only chip
you will use in that socket is the WD 65c02, then the board surgery will
be needed.

All 65c02's are not created equal.

--John

Post by Ian May
Hi John,
on the W65C02S DIP package pin 35 is now the only NC. Pin 36 is BE and
pin 5 is MLB. I'm pretty sure pin 36 needing to be tied high has been
mentioned in the group, but I don't know if it is in the wiki. Track
cutting will be required if it is grounded. Regarding MLB - from the
data sheet - "The Memory Lock (MLB) output may be used to ensure the
integrity of Read-Modify-Write instructions in a multiprocessor
system. Memory Lock indicates the need to defer arbitration of the bus
cycle when MLB is low. Memory Lock is low during the last three cycles
of ASL, DEC, INC, LSR, ROL, ROR, TRB and TSB memory referencing
instructions." The 6809E has an AVMA which performs the same sort of
function going by the data sheet description, but I have never used it.
The W65C02 data sheet also has a specific warning about NC pins - "The
No Connect (NC) pins are not connected internally and should not be
connected externally" - I wonder why if they are not connected internally?
There is an application note here
http://www.westerndesigncenter.com/wdc/AN-002_W65C02S_Replacements.cfm
"Replacement Notes for Obsolete Versions of 6502 8-bit
Microprocessors" which identifies one more pin incompatibility. Pin 1
is now an output VPB - Vector Pull which goes low during interrupt
sequences. I don't recall that being brought up in the group so that
should be left out of the socket as suggested for the Apple machines.
Perhaps there should be a link to that app. note in the wiki? Note
that there are also recommendations for the RDY pin: "[my comments]"
IN SUMMARY: The W65C02S6T (40 pin PDIP) is mostly pin compatible by
* 1.) Cut the trace to VPB (Pin 1). Optionally you can pull this
pin up. [Don't they mean out rather than up???]
* 2.) BE (Pin 36) should be tied directly to VDD (Pin 8).
* 3.) Add a 3.3K Ohm pull-up resistor on RDY (Pin 2) if not being
driven; Add a 3.3K Ohm series current limiting resitor to RDY
(Pin 2) if being driven.[How much does that slow it down?]
* 4.) WDC does not recommend using the SToP or WAIt instruction on
the replacement designs that do not have a current limiting
resistor.
Cheers,
Ian.

Post by Ian May
John, what has been done with SO in the N8VEM and S100 designs?
If it is floating difficulties with maths may occur....

/SO is pulled high. Yes, it is an input, not an output.

Post by Ian May
BE is the Bus Enable pin. When it is low the address, data and
R/W pins are tri-stated. If you are not sharing the buses tie it
high. This function was not implemented on the original 6502.

The data sheets I have for the 65C02 do not have a BE signal.
What pin is it on? I have 3 pins marked NC (no connect): 5, 35,
36. For 6802 use in the socket, pin 35 is connected to Vcc and
pin 36 is connected to GND. There are no option jumpers on these
3 pins.
--John
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Rich Cini

2014-01-30 16:05:35 UTC

Permalink

This is true. There definitely is a difference.

I think you meant Western Design Center rather than Western Digital, though. WDC is Chuck Peddle's company.

Rich Cini
Sent from my iPhone

Ian,
Rich,
The Western Digital 65c02 is a different chip from the Rockwell or California Micro Devices 65c02's. I say this because of the different pin out, which includes pin 5 (MLB) and pin 36 (BE). These signals are not present on the Rockwell or CMD chips.
The pins are connected to allow the 6802 or 6808 to share the same socket on the 6x0x board. With the WD chip, two more jumpers would be needed.
If you are going to swap processors (6502/6802) on the 6x0x board, then the solution below will defeat the 6802. As configured, the board will support the 65c02 from Rockwell or CMD, but not WD. If the only chip you will use in that socket is the WD 65c02, then the board surgery will be needed.
All 65c02's are not created equal.
--John

Post by Ian May
Hi John,
on the W65C02S DIP package pin 35 is now the only NC. Pin 36 is BE and pin 5 is MLB. I'm pretty sure pin 36 needing to be tied high has been mentioned in the group, but I don't know if it is in the wiki. Track cutting will be required if it is grounded. Regarding MLB - from the data sheet - "The Memory Lock (MLB) output may be used to ensure the integrity of Read-Modify-Write instructions in a multiprocessor system. Memory Lock indicates the need to defer arbitration of the bus cycle when MLB is low. Memory Lock is low during the last three cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB and TSB memory referencing instructions." The 6809E has an AVMA which performs the same sort of function going by the data sheet description, but I have never used it.
The W65C02 data sheet also has a specific warning about NC pins - "The No Connect (NC) pins are not connected internally and should not be connected externally" - I wonder why if they are not connected internally?
There is an application note here http://www.westerndesigncenter.com/wdc/AN-002_W65C02S_Replacements.cfm "Replacement Notes for Obsolete Versions of 6502 8-bit Microprocessors" which identifies one more pin incompatibility. Pin 1 is now an output VPB - Vector Pull which goes low during interrupt sequences. I don't recall that being brought up in the group so that should be left out of the socket as suggested for the Apple machines. Perhaps there should be a link to that app. note in the wiki? Note that there are also recommendations for the RDY pin: "[my comments]"
1.) Cut the trace to VPB (Pin 1). Optionally you can pull this pin up. [Don't they mean out rather than up???]
2.) BE (Pin 36) should be tied directly to VDD (Pin 8).
3.) Add a 3.3K Ohm pull-up resistor on RDY (Pin 2) if not being driven; Add a 3.3K Ohm series current limiting resitor to RDY (Pin 2) if being driven.[How much does that slow it down?]
4.) WDC does not recommend using the SToP or WAIt instruction on the replacement designs that do not have a current limiting resistor.
Cheers,
Ian.

Post by Ian May

John, what has been done with SO in the N8VEM and S100 designs? If it is floating difficulties with maths may occur....

/SO is pulled high. Yes, it is an input, not an output.

BE is the Bus Enable pin. When it is low the address, data and R/W pins are tri-stated. If you are not sharing the buses tie it high. This function was not implemented on the original 6502.

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