[N8VEM: 19837] Grant Searle's Multicomputer - the series (now with MP/M 2.1)

[RHKoolaap]

There is now a banked MP/M II V2.1 implementation ready for this
configuration. The XIOS uses the example in the MP/M II System Implementors
Guide as main guidance.

It features 4 terminals and 7 x 48 kilobyte memory segments. There are 3
'Searle standard' disk drives. Drive A: holds the boot volume, drives B:
and C: are assigned a volume during the cold boot process by the
(super)user. I chose for this setup, because using freely mountable volumes
in a multi-user environment seems confusing. All 120 (240) available
volumes can be assigned to B: and C: but mounting the same volume more than
once is rejected.

The Cyclone 2 should be configured with MMU, SD card and 4 serial consoles.
Also you need an interrupt source. You can use the int module from James
Moxham's package, but I just use an extra clock in the systems clock
section.
I feel I don't need a switchable clock, because the processor has an
internal enable flipflop already. All of this fits comfortably in the FPGA
(89% LEs).

Some more remarks on James's INT module: If your TOD (TimeOfDay) clock is
really slow and irregular, the interrupt pulse is too short.
23 Clock pulses (at 50 MHz) is only 11.5 T-cycles @ 25 MHz. Using this
logic the pulse should be at least 46 clocks long @ 25 MHz and 115 @ 10
MHz. Longer is no problem when you disable interrupts at the beginning of
the service routine. I use 255, because I like round numbers.

Even so, the TOD clock will be a bit slow, you can adjust that with the
interrupt timer count (currently 1,000,000) smaller number = faster clock.
Both TOD.COM and SCHED.COM are the millennium fixed version

This version loads a loader program from the system tracks (ROM monitor
S-command), which in turn loads the MPM.SYS file from the indicated boot
volume, just like CP/M-3.

All sources are included, also un-embellished build instructions are
provided.

the installation is 'standard': hexload the loader program, putsys it on a
volume and prepare the volume with the essential files (MPM.SYS, .PRL and
.COM files) or just copy the provided image file on an SD-card.
To change the number of consoles or the number of memory segments,
GENSYS.COM can be used to generate a new MPM.SYS file. The current
configuration is held in the SYSTEM.DAT file, which is included.

On the FPGA configuration: I simplified the VDL somewhat, the SD card now
runs from the CPU clock, so the SDClock section has disappeared. The specs
say the card should run on a 25MHz clock, so this should not be a problem.
The 2 extra consoles run from pins 53,55,57,58,59 and 60, rsp. tx2, rx2,
dtr2, tx3, rx3 and dtr3. You probably can fit 2 terminals and a VGA
display. When I tried I ran 2 LEs short, so some tweaking is required.

here are the files:
http://www.filedropper.com/filemanager/public.php?service=files&t=5bf146616cef542a93502d131b51406e

have fun
RHK

[Alan Cox]

Post by RHKoolaap
Some more remarks on James's INT module: If your TOD (TimeOfDay) clock is
really slow and irregular, the interrupt pulse is too short.

Can you explain this a bit more - eg why its a pulse not a change in
level until the CPU reads a counter register. ?

Post by RHKoolaap
On the FPGA configuration: I simplified the VDL somewhat, the SD card now
runs from the CPU clock, so the SDClock section has disappeared. The specs
say the card should run on a 25MHz clock, so this should not be a problem.

The initial pulse chain and probe are required to be between 100 and
400Khz. The clock is reported by the card but will always be either
20MHz (MMC) or 25MHz (SD). That assumes of course that your socket and
wiring are good enough and have a low enough capacitance and
sufficient shielding to avoid crosstalk. In SPI mode that's fairly
important as you don't have full CRC protection the way most people
drive it.

You could arrange to bitbang the probe logic, or just use a simple
divider off the CPU clock to get ~375Khz I guess.

Alan

[RHKoolaap]

The comment in the interrupt.vhd file states " if (interruptClkCount <
23) and (Qlocal = '1') then -- some instructions need up to 23 cycles
http://www.z80.info/interrup.htm"

following that logic the pulse is too short, even at 25 MHz system clock

I found that the TOD clock would run erratic. The only reason why that
might happen is because interrupts are missed. Increasing the pulse length
made the problem go away. Basically the CPU samples the interrupt line at
the end of the present instruction cycle. This can take between 4 and 23
T-cycles. In order for the interrupt to be reliably detected, the pulse
needs to be at least 23 T-cycles long. The INT module uses a 23 count @ 50
MHz, or 11,5 T-cycles at that speed. However if the system is run at 10
MHz, the interrupt would be only 4.6 T-cycles long, only long enough for
the shortest instruction. This explained the erratic behavior.
disabling the interrupts at the beginning of the service routine ensures
that a longer pulse is seen only once.

For the SD-card I followed the suggestion by Max Scane in his FPGA design.
I did no rigorous research but I checked
"SD Specifications Part 1 Physical Layer Simplified Specification Version
4.10 January 22, 2013" which states:
2. System Features: Default Speed mode: 3.3V signaling, Frequency up to 25
MHz, up to 12.5 MB/sec
which addresses SD mode, and
7.8 Bus Timing: Bus timing is identical to SD mode.
which handles about SPI-mode
Seeing that Max's suggestion was not unreasonable, I just tried using the
CPU clock (16.6 MHz) making the SPI clock 8.3 MHz.
and it works well enough (and notably faster). As for layout, I'm using
James Moxham's Cyclone2v108 board.

Does that answer the questions?

RHK

Post by Alan Cox

Post by RHKoolaap
Some more remarks on James's INT module: If your TOD (TimeOfDay) clock

is

Post by RHKoolaap
really slow and irregular, the interrupt pulse is too short.

Can you explain this a bit more - eg why its a pulse not a change in
level until the CPU reads a counter register. ?

Post by RHKoolaap
On the FPGA configuration: I simplified the VDL somewhat, the SD card

now

Post by RHKoolaap
runs from the CPU clock, so the SDClock section has disappeared. The

specs

Post by RHKoolaap
say the card should run on a 25MHz clock, so this should not be a

problem.
The initial pulse chain and probe are required to be between 100 and
400Khz. The clock is reported by the card but will always be either
20MHz (MMC) or 25MHz (SD). That assumes of course that your socket and
wiring are good enough and have a low enough capacitance and
sufficient shielding to avoid crosstalk. In SPI mode that's fairly
important as you don't have full CRC protection the way most people
drive it.
You could arrange to bitbang the probe logic, or just use a simple
divider off the CPU clock to get ~375Khz I guess.
Alan

[Alan Cox]

Post by RHKoolaap
The comment in the interrupt.vhd file states " if (interruptClkCount <
23) and (Qlocal = '1') then -- some instructions need up to 23 cycles
http://www.z80.info/interrup.htm"
following that logic the pulse is too short, even at 25 MHz system clock
I found that the TOD clock would run erratic. The only reason why that might
happen is because interrupts are missed. Increasing the pulse length made
the problem go away. Basically the CPU samples the interrupt line at the end
of the present instruction cycle. This can take between 4 and 23 T-cycles.
In order for the interrupt to be reliably detected, the pulse needs to be
T-cycles at that speed. However if the system is run at 10 MHz, the
interrupt would be only 4.6 T-cycles long, only long enough for the shortest
instruction. This explained the erratic behavior.
disabling the interrupts at the beginning of the service routine ensures
that a longer pulse is seen only once.

Ok I'm missing something here - why is it a pulse, you would normally
assert an IRQ on a Z80 and leave it asserted until the CPU performed
some action which de-asserted it. That way you never miss anything
even shared.

Post by RHKoolaap
For the SD-card I followed the suggestion by Max Scane in his FPGA design. I
did no rigorous research but I checked
"SD Specifications Part 1 Physical Layer Simplified Specification Version
2. System Features: Default Speed mode: 3.3V signaling, Frequency up to 25
MHz, up to 12.5 MB/sec
which addresses SD mode, and
7.8 Bus Timing: Bus timing is identical to SD mode.
which handles about SPI-mode

The specification says that the initial move into SPI mode and the
probing should be doing t a much lower speed range. Only then do you
switch to 20 or 25Mhz according to the card (and for complicated
reasons in non SPI mode to other possible speeds)

You are not supposed to talk above 400KHz until after you have send CMD59.

So normally you do

400Khz (or a bit less)
Drop CS
Issue 80 pulses
Raise CS
CMD 0
expect 0x01 (may need to repeat init sequences)
CMD 1
etc
CMD59
get the reply

Switch to 20 or 25MHz

Do I/O at speed

[RHKoolaap]

Post by RHKoolaap

Post by RHKoolaap
The comment in the interrupt.vhd file states " if

(interruptClkCount <

Post by RHKoolaap
23) and (Qlocal = '1') then -- some instructions need up to 23 cycles
http://www.z80.info/interrup.htm"
following that logic the pulse is too short, even at 25 MHz system clock
I found that the TOD clock would run erratic. The only reason why that

might

Post by RHKoolaap
happen is because interrupts are missed. Increasing the pulse length

made

Post by RHKoolaap
the problem go away. Basically the CPU samples the interrupt line at the

end

Post by RHKoolaap
of the present instruction cycle. This can take between 4 and 23

T-cycles.

Post by RHKoolaap
In order for the interrupt to be reliably detected, the pulse needs to

be
11,5

Post by RHKoolaap
T-cycles at that speed. However if the system is run at 10 MHz, the
interrupt would be only 4.6 T-cycles long, only long enough for the

shortest

Post by RHKoolaap
instruction. This explained the erratic behavior.
disabling the interrupts at the beginning of the service routine ensures
that a longer pulse is seen only once.

Ok I'm missing something here - why is it a pulse, you would normally
assert an IRQ on a Z80 and leave it asserted until the CPU performed
some action which de-asserted it. That way you never miss anything
even shared.

you are very right, off course But in the current configuration this is not
implemented.
the 50 Hz clock is just an oscillator, 10 microseconds down, 20 ms up (ok,
19990 us). In this case more complicated logic is not necessary. The reason
why is a shortage of logic elements in the FPLA, off course. The challenge
is to get everything to work with limited resources. Some shortcuts are
required.

Post by RHKoolaap

Post by RHKoolaap
For the SD-card I followed the suggestion by Max Scane in his FPGA

design. I

Post by RHKoolaap
did no rigorous research but I checked
"SD Specifications Part 1 Physical Layer Simplified Specification

Version

Post by RHKoolaap
2. System Features: Default Speed mode: 3.3V signaling, Frequency up to

25

Post by RHKoolaap
MHz, up to 12.5 MB/sec
which addresses SD mode, and
7.8 Bus Timing: Bus timing is identical to SD mode.
which handles about SPI-mode

The specification says that the initial move into SPI mode and the
probing should be doing t a much lower speed range. Only then do you
switch to 20 or 25Mhz according to the card (and for complicated
reasons in non SPI mode to other possible speeds)
You are not supposed to talk above 400KHz until after you have send CMD59.
So normally you do
400Khz (or a bit less)
Drop CS
Issue 80 pulses
Raise CS
CMD 0
expect 0x01 (may need to repeat init sequences)
CMD 1
etc
CMD59
get the reply
Switch to 20 or 25MHz
Do I/O at speed

Ok, I'm a bit out of my league here, In my understanding the SD-controller
takes care of that. I am just talking about the clock input of that unit.

[Neal Crook]

Post by RHKoolaap
Ok, I'm a bit out of my league here, In my understanding the

SD-controller takes care of that. I am just talking about the clock input
of that unit. > "SD Specifications Part 1 Physical Layer

if you're using Grant's VHDL unchanged (hard to tell because it is not part
of your .zip) the SD controller doesn't do any messing about with the
clock. It simply generates an output clock (sdSCLK) at half the rate of the
input clock. Strictly speaking, sdSCLK is an output of the state machine
clocked from the input clock, so (from a timing analysis point of view) is
is a "signal" rather than a clock.

Hence it sounds as though you're running well out of spec. for the initial
"negotiation" that Alan describes. If it works for you, then fine (but I
suggest not going into mass production without rigorous testing!)

Notwithstanding that, thanks for sharing!

regards,

Neal.

[RHKoolaap]

Good to know, Btw, If I'm not including it I didn't change it. The package
overlays Grant's design.

Not only does it work, it works very well. It speeds up performance and
makes the board feel very "zippy". I do all my building on the board itself
and have found no errors.
I'm not mass producing, It's a hobby :-) Nobody in his right mind would use
something like this in anything mission critical, now would they?
If something goes haywire, It sure is a good place to start looking,
though...

I really need to go learn more about VHDL in detail though. Thank you (and
Alan) all for the guidance.

Post by Neal Crook

Post by RHKoolaap
Ok, I'm a bit out of my league here, In my understanding the

SD-controller takes care of that. I am just talking about the clock input
of that unit. > "SD Specifications Part 1 Physical Layer
if you're using Grant's VHDL unchanged (hard to tell because it is not
part of your .zip) the SD controller doesn't do any messing about with the
clock. It simply generates an output clock (sdSCLK) at half the rate of the
input clock. Strictly speaking, sdSCLK is an output of the state machine
clocked from the input clock, so (from a timing analysis point of view) is
is a "signal" rather than a clock.
Hence it sounds as though you're running well out of spec. for the initial
"negotiation" that Alan describes. If it works for you, then fine (but I
suggest not going into mass production without rigorous testing!)
Notwithstanding that, thanks for sharing!
regards,
Neal.

[Kip Koon]

Hi RHKoolaap,

You package is quite impressive! I live in the USA, so I need a 60 HZ configuration.

Do you have a 4 Serial port version of the Multicomp PCB? I only have a 2 serial port v1.09 Multicomp PCB setup currently. I’m waiting for the new test board to get here.

Do I need to wire up some more ports?

If I ignore the 3rd and 4th port, will the v1.09 Multicomp board and FPGA Module be ok?

Should I eliminate port 3 and 4?

Do you have pictures and a schematic of your particular Multicomp setup especially the 3rd and 4th serial ports. A 4 user version would be most interesting. I’d like to get this going tonight if possible. Thanks a bunch for your hard work. I can hardly wait to start putting CP/M dsk files onto all those 240 virtual disk drives! Speaking of which, how do I get a CP/M or MP/M dsk file onto one of the blank drives? Take care my friend!



Kip Koon

***@sc.rr.com

http://www.cocopedia.com/wiki/index.php/Kip_Koon





From: ***@googlegroups.com [mailto:***@googlegroups.com] On Behalf Of RHKoolaap
Sent: Sunday, July 12, 2015 2:54 PM
To: ***@googlegroups.com
Subject: [N8VEM: 19837] Grant Searle's Multicomputer - the series (now with MP/M 2.1)



There is now a banked MP/M II V2.1 implementation ready for this configuration. The XIOS uses the example in the MP/M II System Implementors Guide as main guidance.



It features 4 terminals and 7 x 48 kilobyte memory segments. There are 3 'Searle standard' disk drives. Drive A: holds the boot volume, drives B: and C: are assigned a volume during the cold boot process by the (super)user. I chose for this setup, because using freely mountable volumes in a multi-user environment seems confusing. All 120 (240) available volumes can be assigned to B: and C: but mounting the same volume more than once is rejected.



The Cyclone 2 should be configured with MMU, SD card and 4 serial consoles. Also you need an interrupt source. You can use the int module from James Moxham's package, but I just use an extra clock in the systems clock section.

I feel I don't need a switchable clock, because the processor has an internal enable flipflop already. All of this fits comfortably in the FPGA (89% LEs).



Some more remarks on James's INT module: If your TOD (TimeOfDay) clock is really slow and irregular, the interrupt pulse is too short.

23 Clock pulses (at 50 MHz) is only 11.5 T-cycles @ 25 MHz. Using this logic the pulse should be at least 46 clocks long @ 25 MHz and 115 @ 10 MHz. Longer is no problem when you disable interrupts at the beginning of the service routine. I use 255, because I like round numbers.



Even so, the TOD clock will be a bit slow, you can adjust that with the interrupt timer count (currently 1,000,000) smaller number = faster clock. Both TOD.COM and SCHED.COM are the millennium fixed version



This version loads a loader program from the system tracks (ROM monitor S-command), which in turn loads the MPM.SYS file from the indicated boot volume, just like CP/M-3.



All sources are included, also un-embellished build instructions are provided.



the installation is 'standard': hexload the loader program, putsys it on a volume and prepare the volume with the essential files (MPM.SYS, .PRL and .COM files) or just copy the provided image file on an SD-card.

To change the number of consoles or the number of memory segments, GENSYS.COM can be used to generate a new MPM.SYS file. The current configuration is held in the SYSTEM.DAT file, which is included.



On the FPGA configuration: I simplified the VDL somewhat, the SD card now runs from the CPU clock, so the SDClock section has disappeared. The specs say the card should run on a 25MHz clock, so this should not be a problem. The 2 extra consoles run from pins 53,55,57,58,59 and 60, rsp. tx2, rx2, dtr2, tx3, rx3 and dtr3. You probably can fit 2 terminals and a VGA display. When I tried I ran 2 LEs short, so some tweaking is required.



here are the files:

http://www.filedropper.com/filemanager/public.php?service=files <http://www.filedropper.com/filemanager/public.php?service=files&t=5bf146616cef542a93502d131b51406e> &t=5bf146616cef542a93502d131b51406e



have fun

RHK
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[RHKoolaap]

Hi Kip
If you want to run the board at 60 Hz, you can adjust the interrupt clock.
use something like *933333* (5/6th of 1,000,000)
then you need to change the value of tickps in BNKXIOS.ASM (tickps equ *50* ;
ticks per second) into *60* and rebuild. Finally you need to re-run
GENSYS.COM and type *#60* (or 3C) in the appropriate place.

I don't see why you need a 60 Hz clock for any other reason than
sentimental ones though, the interrupt is not used for anything else.

Yes you can ignore the not used consoles (users are AFK :-). I tied the
inputs to a weak pullup. I do it all the time. The system will spend
resources polling them though. You can prevent that by running GENSYS and
type the number of consoles you want. please make a backup of SYSTEM.DAT
before you run GENSYS.
The pins should be available on the touchscreen connector, I used 2 ftdi
modules and patchwires (only 3 wires each, because I run usb hub and board
from the same 5v power supply)

fast install: unzip the 5DISK.ZIP to 5DISK.IMG then go to this website
:http://www.chrysocome.net/rawwrite and obtain rawwrite for windows. that
will probably work. If not, there is also a dd for windows on the same
website, That WILL work, but I get confused about windows physical devices.
I am not a windows user, so I should not be the one to tell you how.
Careful though, dd can overwrite (part of) your harddisk if you make
mistakes. It happened to me once :-(

the command in linux is dd if=5disk.img of=/dev/sdb (/dev/sdb being the
SD-card)

this creates the first 5 volumes, you can add the rest with the monitor I
command. I6 creates the 6th volume. to put CP/M to on the system track type
L2 (load systemtrack volume 2) P6 (put system track on volume 6)
to put CP/M-3 you need to:

L3 (load loader)

P6 (write on volume 6)
S3 (start CP/M3)
mount b:6 (mount volume 6 on drive B:)
ppip *.* b: (write all user 0 files to drive B:)
reset (return to monitor)
S6 (start in new volume)


for MP/M you need to use volume 4 as source and mount B: on volume 6 during
startup

have fun.
RHK

Post by Kip Koon
Hi RHKoolaap,
You package is quite impressive! I live in the USA, so I need a 60 HZ configuration.
Do you have a 4 Serial port version of the Multicomp PCB? I only have a 2
serial port v1.09 Multicomp PCB setup currently. I’m waiting for the new
test board to get here.
Do I need to wire up some more ports?
If I ignore the 3rd and 4th port, will the v1.09 Multicomp board and FPGA Module be ok?
Should I eliminate port 3 and 4?
Do you have pictures and a schematic of your particular Multicomp setup
especially the 3rd and 4th serial ports. A 4 user version would be most
interesting. I’d like to get this going tonight if possible. Thanks a
bunch for your hard work. I can hardly wait to start putting CP/M dsk
files onto all those 240 virtual disk drives! Speaking of which, how do I
get a CP/M or MP/M dsk file onto one of the blank drives? Take care my
friend!
Kip Koon
http://www.cocopedia.com/wiki/index.php/Kip_Koon
*Sent:* Sunday, July 12, 2015 2:54 PM
*Subject:* [N8VEM: 19837] Grant Searle's Multicomputer - the series (now
with MP/M 2.1)
There is now a banked MP/M II V2.1 implementation ready for this
configuration. The XIOS uses the example in the MP/M II System Implementors
Guide as main guidance.
It features 4 terminals and 7 x 48 kilobyte memory segments. There are 3
and C: are assigned a volume during the cold boot process by the
(super)user. I chose for this setup, because using freely mountable volumes
in a multi-user environment seems confusing. All 120 (240) available
volumes can be assigned to B: and C: but mounting the same volume more than
once is rejected.
The Cyclone 2 should be configured with MMU, SD card and 4 serial
consoles. Also you need an interrupt source. You can use the int module
from James Moxham's package, but I just use an extra clock in the systems
clock section.
I feel I don't need a switchable clock, because the processor has an
internal enable flipflop already. All of this fits comfortably in the FPGA
(89% LEs).
Some more remarks on James's INT module: If your TOD (TimeOfDay) clock is
really slow and irregular, the interrupt pulse is too short.
MHz. Longer is no problem when you disable interrupts at the beginning of
the service routine. I use 255, because I like round numbers.
Even so, the TOD clock will be a bit slow, you can adjust that with the
interrupt timer count (currently 1,000,000) smaller number = faster clock.
Both TOD.COM and SCHED.COM are the millennium fixed version
This version loads a loader program from the system tracks (ROM monitor
S-command), which in turn loads the MPM.SYS file from the indicated boot
volume, just like CP/M-3.
All sources are included, also un-embellished build instructions are provided.
the installation is 'standard': hexload the loader program, putsys it on a
volume and prepare the volume with the essential files (MPM.SYS, .PRL and
.COM files) or just copy the provided image file on an SD-card.
To change the number of consoles or the number of memory segments,
GENSYS.COM can be used to generate a new MPM.SYS file. The current
configuration is held in the SYSTEM.DAT file, which is included.
On the FPGA configuration: I simplified the VDL somewhat, the SD card now
runs from the CPU clock, so the SDClock section has disappeared. The specs
say the card should run on a 25MHz clock, so this should not be a problem.
The 2 extra consoles run from pins 53,55,57,58,59 and 60, rsp. tx2, rx2,
dtr2, tx3, rx3 and dtr3. You probably can fit 2 terminals and a VGA
display. When I tried I ran 2 LEs short, so some tweaking is required.
http://www.filedropper.com/filemanager/public.php?service=files&t=5bf146616cef542a93502d131b51406e
have fun
RHK
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[Kip Koon]

Hi RHKoolaap,

Well, if I don’t need to change to 60HZ for the Interrupt, then I’ll just leave it like it is. For the first test on my Multicomp, I’ll leave everything like it is. Later on, I would like to connect up the 3rd and 4th serial ports as I do have 3 TTL to Serial RS-232 modules. I figured they would eventually come in handy. :) Would you please give me the pin configuration on the Touchscreen interface for the two extra serial ports and their functions so I can wire this all up? I would appreciate it very much. Thank you. Take care my friend.



Kip Koon

***@sc.rr.com

http://www.cocopedia.com/wiki/index.php/Kip_Koon





From: ***@googlegroups.com [mailto:***@googlegroups.com] On Behalf Of RHKoolaap
Sent: Monday, July 13, 2015 3:17 AM
To: ***@googlegroups.com
Subject: Re: [N8VEM: 19842] Grant Searle's Multicomputer - the series (now with MP/M 2.1)



Hi Kip

If you want to run the board at 60 Hz, you can adjust the interrupt clock. use something like 933333 (5/6th of 1,000,000)

then you need to change the value of tickps in BNKXIOS.ASM (tickps equ 50 ; ticks per second) into 60 and rebuild. Finally you need to re-run GENSYS.COM and type #60 (or 3C) in the appropriate place.



I don't see why you need a 60 Hz clock for any other reason than sentimental ones though, the interrupt is not used for anything else.



Yes you can ignore the not used consoles (users are AFK :-). I tied the inputs to a weak pullup. I do it all the time. The system will spend resources polling them though. You can prevent that by running GENSYS and type the number of consoles you want. please make a backup of SYSTEM.DAT before you run GENSYS.

The pins should be available on the touchscreen connector, I used 2 ftdi modules and patchwires (only 3 wires each, because I run usb hub and board from the same 5v power supply)



fast install: unzip the 5DISK.ZIP to 5DISK.IMG then go to this website :http://www.chrysocome.net/rawwrite and obtain rawwrite for windows. that will probably work. If not, there is also a dd for windows on the same website, That WILL work, but I get confused about windows physical devices. I am not a windows user, so I should not be the one to tell you how. Careful though, dd can overwrite (part of) your harddisk if you make mistakes. It happened to me once :-(



the command in linux is dd if=5disk.img of=/dev/sdb (/dev/sdb being the SD-card)



this creates the first 5 volumes, you can add the rest with the monitor I command. I6 creates the 6th volume. to put CP/M to on the system track type L2 (load systemtrack volume 2) P6 (put system track on volume 6)

to put CP/M-3 you need to:

L3 (load loader)

P6 (write on volume 6)

S3 (start CP/M3)

mount b:6 (mount volume 6 on drive B:)

ppip *.* b: (write all user 0 files to drive B:)

reset (return to monitor)

S6 (start in new volume)



for MP/M you need to use volume 4 as source and mount B: on volume 6 during startup



have fun.

RHK



On Monday, July 13, 2015 at 7:44:48 AM UTC+2, computerdoc wrote:

Hi RHKoolaap,

You package is quite impressive! I live in the USA, so I need a 60 HZ configuration.

Do you have a 4 Serial port version of the Multicomp PCB? I only have a 2 serial port v1.09 Multicomp PCB setup currently. I’m waiting for the new test board to get here.

Do I need to wire up some more ports?

If I ignore the 3rd and 4th port, will the v1.09 Multicomp board and FPGA Module be ok?

Should I eliminate port 3 and 4?

Do you have pictures and a schematic of your particular Multicomp setup especially the 3rd and 4th serial ports. A 4 user version would be most interesting. I’d like to get this going tonight if possible. Thanks a bunch for your hard work. I can hardly wait to start putting CP/M dsk files onto all those 240 virtual disk drives! Speaking of which, how do I get a CP/M or MP/M dsk file onto one of the blank drives? Take care my friend!



Kip Koon

***@sc.rr.com <javascript:>

http://www.cocopedia.com/wiki/index.php/Kip_Koon





From: ***@googlegroups.com <javascript:> [mailto:***@googlegroups.com <javascript:> ] On Behalf Of RHKoolaap
Sent: Sunday, July 12, 2015 2:54 PM
To: ***@googlegroups.com <javascript:>
Subject: [N8VEM: 19837] Grant Searle's Multicomputer - the series (now with MP/M 2.1)



There is now a banked MP/M II V2.1 implementation ready for this configuration. The XIOS uses the example in the MP/M II System Implementors Guide as main guidance.



It features 4 terminals and 7 x 48 kilobyte memory segments. There are 3 'Searle standard' disk drives. Drive A: holds the boot volume, drives B: and C: are assigned a volume during the cold boot process by the (super)user. I chose for this setup, because using freely mountable volumes in a multi-user environment seems confusing. All 120 (240) available volumes can be assigned to B: and C: but mounting the same volume more than once is rejected.



The Cyclone 2 should be configured with MMU, SD card and 4 serial consoles. Also you need an interrupt source. You can use the int module from James Moxham's package, but I just use an extra clock in the systems clock section.

I feel I don't need a switchable clock, because the processor has an internal enable flipflop already. All of this fits comfortably in the FPGA (89% LEs).



Some more remarks on James's INT module: If your TOD (TimeOfDay) clock is really slow and irregular, the interrupt pulse is too short.

23 Clock pulses (at 50 MHz) is only 11.5 T-cycles @ 25 MHz. Using this logic the pulse should be at least 46 clocks long @ 25 MHz and 115 @ 10 MHz. Longer is no problem when you disable interrupts at the beginning of the service routine. I use 255, because I like round numbers.



Even so, the TOD clock will be a bit slow, you can adjust that with the interrupt timer count (currently 1,000,000) smaller number = faster clock. Both TOD.COM and SCHED.COM are the millennium fixed version



This version loads a loader program from the system tracks (ROM monitor S-command), which in turn loads the MPM.SYS file from the indicated boot volume, just like CP/M-3.



All sources are included, also un-embellished build instructions are provided.



the installation is 'standard': hexload the loader program, putsys it on a volume and prepare the volume with the essential files (MPM.SYS, .PRL and .COM files) or just copy the provided image file on an SD-card.

To change the number of consoles or the number of memory segments, GENSYS.COM can be used to generate a new MPM.SYS file. The current configuration is held in the SYSTEM.DAT file, which is included.



On the FPGA configuration: I simplified the VDL somewhat, the SD card now runs from the CPU clock, so the SDClock section has disappeared. The specs say the card should run on a 25MHz clock, so this should not be a problem. The 2 extra consoles run from pins 53,55,57,58,59 and 60, rsp. tx2, rx2, dtr2, tx3, rx3 and dtr3. You probably can fit 2 terminals and a VGA display. When I tried I ran 2 LEs short, so some tweaking is required.



here are the files:

http://www.filedropper.com/filemanager/public.php?service=files <http://www.filedropper.com/filemanager/public.php?service=files&t=5bf146616cef542a93502d131b51406e> &t=5bf146616cef542a93502d131b51406e



have fun

RHK
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[RHKoolaap]

Don't you have the schematics for your 109 board? Ok, here comes
read in 4 colums: board signal, FPGA PIN, Touchscreen pin, serial I/F pin

tx2, 53, 29, RXI
rx2, 55, 33, TXO
dtr2, 57, 18, CTS

tx3, 58, 20, RXI
rx3, 59, 22, TXO
dtr3, 60, 26, CTS

on the 108 board the touchscreen pins line up better:

tx2, 53, 06 , RXI
rx2, 55, 08, TXO
dtr2, 57, 10, CTS

tx3, 58, 12, RXI
rx3, 59, 14, TXO
dtr3, 60, 16, CTS

if you need a ground pin, you can use touchscreen pin 1 (both boards)

feel free to reassign the pins so they line up better your board. (or use
the 108 board, You have one - I sent it to you :-)

RHK

Post by Kip Koon
Hi RHKoolaap,
Well, if I don’t need to change to 60HZ for the Interrupt, then I’ll just
leave it like it is. For the first test on my Multicomp, I’ll leave
everything like it is. Later on, I would like to connect up the 3rd and 4
th serial ports as I do have 3 TTL to Serial RS-232 modules. I figured
they would eventually come in handy. :) Would you please give me the pin
configuration on the Touchscreen interface for the two extra serial ports
and their functions so I can wire this all up? I would appreciate it very
much. Thank you. Take care my friend.
Kip Koon
http://www.cocopedia.com/wiki/index.php/Kip_Koon
*Sent:* Monday, July 13, 2015 3:17 AM
*Subject:* Re: [N8VEM: 19842] Grant Searle's Multicomputer - the series
(now with MP/M 2.1)
Hi Kip
If you want to run the board at 60 Hz, you can adjust the interrupt clock.
use something like *933333* (5/6th of 1,000,000)
then you need to change the value of tickps in BNKXIOS.ASM (tickps equ
*50* ; ticks per second) into *60* and rebuild. Finally you need
to re-run GENSYS.COM and type *#60* (or 3C) in the appropriate place.
I don't see why you need a 60 Hz clock for any other reason than
sentimental ones though, the interrupt is not used for anything else.
Yes you can ignore the not used consoles (users are AFK :-). I tied the
inputs to a weak pullup. I do it all the time. The system will spend
resources polling them though. You can prevent that by running GENSYS and
type the number of consoles you want. please make a backup of SYSTEM.DAT
before you run GENSYS.
The pins should be available on the touchscreen connector, I used 2 ftdi
modules and patchwires (only 3 wires each, because I run usb hub and board
from the same 5v power supply)
http://www.chrysocome.net/rawwrite and obtain rawwrite for windows. that
will probably work. If not, there is also a dd for windows on the same
website, That WILL work, but I get confused about windows physical devices.
I am not a windows user, so I should not be the one to tell you how.
Careful though, dd can overwrite (part of) your harddisk if you make
mistakes. It happened to me once :-(
the command in linux is dd if=5disk.img of=/dev/sdb (/dev/sdb being the SD-card)
this creates the first 5 volumes, you can add the rest with the monitor I
command. I6 creates the 6th volume. to put CP/M to on the system track type
L2 (load systemtrack volume 2) P6 (put system track on volume 6)
L3 (load loader)
P6 (write on volume 6)
S3 (start CP/M3)
mount b:6 (mount volume 6 on drive B:)
ppip *.* b: (write all user 0 files to drive B:)
reset (return to monitor)
S6 (start in new volume)
for MP/M you need to use volume 4 as source and mount B: on volume 6 during startup
have fun.
RHK
Hi RHKoolaap,
You package is quite impressive! I live in the USA, so I need a 60 HZ configuration.
Do you have a 4 Serial port version of the Multicomp PCB? I only have a 2
serial port v1.09 Multicomp PCB setup currently. I’m waiting for the new
test board to get here.
Do I need to wire up some more ports?
If I ignore the 3rd and 4th port, will the v1.09 Multicomp board and FPGA Module be ok?
Should I eliminate port 3 and 4?
Do you have pictures and a schematic of your particular Multicomp setup
especially the 3rd and 4th serial ports. A 4 user version would be most
interesting. I’d like to get this going tonight if possible. Thanks a
bunch for your hard work. I can hardly wait to start putting CP/M dsk
files onto all those 240 virtual disk drives! Speaking of which, how do I
get a CP/M or MP/M dsk file onto one of the blank drives? Take care my
friend!
Kip Koon
http://www.cocopedia.com/wiki/index.php/Kip_Koon
Of *RHKoolaap
*Sent:* Sunday, July 12, 2015 2:54 PM
*Subject:* [N8VEM: 19837] Grant Searle's Multicomputer - the series (now
with MP/M 2.1)
There is now a banked MP/M II V2.1 implementation ready for this
configuration. The XIOS uses the example in the MP/M II System Implementors
Guide as main guidance.
It features 4 terminals and 7 x 48 kilobyte memory segments. There are 3
and C: are assigned a volume during the cold boot process by the
(super)user. I chose for this setup, because using freely mountable volumes
in a multi-user environment seems confusing. All 120 (240) available
volumes can be assigned to B: and C: but mounting the same volume more than
once is rejected.
The Cyclone 2 should be configured with MMU, SD card and 4 serial
consoles. Also you need an interrupt source. You can use the int module
from James Moxham's package, but I just use an extra clock in the systems
clock section.
I feel I don't need a switchable clock, because the processor has an
internal enable flipflop already. All of this fits comfortably in the FPGA
(89% LEs).
Some more remarks on James's INT module: If your TOD (TimeOfDay) clock is
really slow and irregular, the interrupt pulse is too short.
MHz. Longer is no problem when you disable interrupts at the beginning of
the service routine. I use 255, because I like round numbers.
Even so, the TOD clock will be a bit slow, you can adjust that with the
interrupt timer count (currently 1,000,000) smaller number = faster clock.
Both TOD.COM and SCHED.COM are the millennium fixed version
This version loads a loader program from the system tracks (ROM monitor
S-command), which in turn loads the MPM.SYS file from the indicated boot
volume, just like CP/M-3.
All sources are included, also un-embellished build instructions are provided.
the installation is 'standard': hexload the loader program, putsys it on a
volume and prepare the volume with the essential files (MPM.SYS, .PRL and
.COM files) or just copy the provided image file on an SD-card.
To change the number of consoles or the number of memory segments,
GENSYS.COM can be used to generate a new MPM.SYS file. The current
configuration is held in the SYSTEM.DAT file, which is included.
On the FPGA configuration: I simplified the VDL somewhat, the SD card now
runs from the CPU clock, so the SDClock section has disappeared. The specs
say the card should run on a 25MHz clock, so this should not be a problem.
The 2 extra consoles run from pins 53,55,57,58,59 and 60, rsp. tx2, rx2,
dtr2, tx3, rx3 and dtr3. You probably can fit 2 terminals and a VGA
display. When I tried I ran 2 LEs short, so some tweaking is required.
http://www.filedropper.com/filemanager/public.php?service=files&t=5bf146616cef542a93502d131b51406e
have fun
RHK
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[RHKoolaap]

Hi Kip

your question made me think though. I now dynamically assign the ticks per
second from the sysdat page. no need to rebuild.
will be available in the next update.
RHK

Post by RHKoolaap
Hi Kip
If you want to run the board at 60 Hz, you can adjust the interrupt clock.
use something like *933333* (5/6th of 1,000,000)
then you need to change the value of tickps in BNKXIOS.ASM (tickps equ
*50* ; ticks per second) into *60* and rebuild. Finally you need to
re-run GENSYS.COM and type *#60* (or 3C) in the appropriate place.
I don't see why you need a 60 Hz clock for any other reason than
sentimental ones though, the interrupt is not used for anything else.
Yes you can ignore the not used consoles (users are AFK :-). I tied the
inputs to a weak pullup. I do it all the time. The system will spend
resources polling them though. You can prevent that by running GENSYS and
type the number of consoles you want. please make a backup of SYSTEM.DAT
before you run GENSYS.
The pins should be available on the touchscreen connector, I used 2 ftdi
modules and patchwires (only 3 wires each, because I run usb hub and board
from the same 5v power supply)
http://www.chrysocome.net/rawwrite and obtain rawwrite for windows. that
will probably work. If not, there is also a dd for windows on the same
website, That WILL work, but I get confused about windows physical devices.
I am not a windows user, so I should not be the one to tell you how.
Careful though, dd can overwrite (part of) your harddisk if you make
mistakes. It happened to me once :-(
the command in linux is dd if=5disk.img of=/dev/sdb (/dev/sdb being the
SD-card)
this creates the first 5 volumes, you can add the rest with the monitor I
command. I6 creates the 6th volume. to put CP/M to on the system track type
L2 (load systemtrack volume 2) P6 (put system track on volume 6)
L3 (load loader)
P6 (write on volume 6)
S3 (start CP/M3)
mount b:6 (mount volume 6 on drive B:)
ppip *.* b: (write all user 0 files to drive B:)
reset (return to monitor)
S6 (start in new volume)
for MP/M you need to use volume 4 as source and mount B: on volume 6
during startup
have fun.
RHK

Post by Kip Koon
Hi RHKoolaap,
You package is quite impressive! I live in the USA, so I need a 60 HZ configuration.
Do you have a 4 Serial port version of the Multicomp PCB? I only have a
2 serial port v1.09 Multicomp PCB setup currently. I’m waiting for the new
test board to get here.
Do I need to wire up some more ports?
If I ignore the 3rd and 4th port, will the v1.09 Multicomp board and FPGA Module be ok?
Should I eliminate port 3 and 4?
Do you have pictures and a schematic of your particular Multicomp setup
especially the 3rd and 4th serial ports. A 4 user version would be most
interesting. I’d like to get this going tonight if possible. Thanks a
bunch for your hard work. I can hardly wait to start putting CP/M dsk
files onto all those 240 virtual disk drives! Speaking of which, how do I
get a CP/M or MP/M dsk file onto one of the blank drives? Take care my
friend!
Kip Koon
http://www.cocopedia.com/wiki/index.php/Kip_Koon
Behalf Of *RHKoolaap
*Sent:* Sunday, July 12, 2015 2:54 PM
*Subject:* [N8VEM: 19837] Grant Searle's Multicomputer - the series (now
with MP/M 2.1)
There is now a banked MP/M II V2.1 implementation ready for this
configuration. The XIOS uses the example in the MP/M II System Implementors
Guide as main guidance.
It features 4 terminals and 7 x 48 kilobyte memory segments. There are 3
and C: are assigned a volume during the cold boot process by the
(super)user. I chose for this setup, because using freely mountable volumes
in a multi-user environment seems confusing. All 120 (240) available
volumes can be assigned to B: and C: but mounting the same volume more than
once is rejected.
The Cyclone 2 should be configured with MMU, SD card and 4 serial
consoles. Also you need an interrupt source. You can use the int module
from James Moxham's package, but I just use an extra clock in the systems
clock section.
I feel I don't need a switchable clock, because the processor has an
internal enable flipflop already. All of this fits comfortably in the FPGA
(89% LEs).
Some more remarks on James's INT module: If your TOD (TimeOfDay) clock
is really slow and irregular, the interrupt pulse is too short.
MHz. Longer is no problem when you disable interrupts at the beginning of
the service routine. I use 255, because I like round numbers.
Even so, the TOD clock will be a bit slow, you can adjust that with the
interrupt timer count (currently 1,000,000) smaller number = faster clock.
Both TOD.COM and SCHED.COM are the millennium fixed version
This version loads a loader program from the system tracks (ROM monitor
S-command), which in turn loads the MPM.SYS file from the indicated boot
volume, just like CP/M-3.
All sources are included, also un-embellished build instructions are provided.
the installation is 'standard': hexload the loader program, putsys it on
a volume and prepare the volume with the essential files (MPM.SYS, .PRL and
.COM files) or just copy the provided image file on an SD-card.
To change the number of consoles or the number of memory segments,
GENSYS.COM can be used to generate a new MPM.SYS file. The current
configuration is held in the SYSTEM.DAT file, which is included.
On the FPGA configuration: I simplified the VDL somewhat, the SD card now
runs from the CPU clock, so the SDClock section has disappeared. The specs
say the card should run on a 25MHz clock, so this should not be a problem.
The 2 extra consoles run from pins 53,55,57,58,59 and 60, rsp. tx2, rx2,
dtr2, tx3, rx3 and dtr3. You probably can fit 2 terminals and a VGA
display. When I tried I ran 2 LEs short, so some tweaking is required.
http://www.filedropper.com/filemanager/public.php?service=files&t=5bf146616cef542a93502d131b51406e
have fun
RHK
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[Alan Cox]

Thanks - that all makes sense now.