[N8VEM: 19281] Zeta SBC V2

[Sergey]

Hi,

For the last few weeks I've been working on redesign of Zeta SBC. While the
redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.

How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).

What's new:
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.

The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.

More information about this project:
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2

Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.

Thanks,
Sergey

[J. Alexander Jacocks]

Sergey,

As a great fan of the Zeta v1, I'd definitely like one of these boards.

- Alex

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
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[Paul Birkel]

I'm in the same camp as Alex. Please add me to the list for one board
Sergey :->.

Post by J. Alexander Jacocks
Sergey,
As a great fan of the Zeta v1, I'd definitely like one of these boards.
- Alex

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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[Wolfgang Kabatzke]

Hi,

looks great! I read with big interest that You now use an CTC for clock
generating on the SBC. This is simialar to my ECB-ModPrn. Which OS is
running and use You RomWBW? If there is more time I plan to install an
interrupt driven driver for ECB-ModPrn and the development of an low
cost version of Centronics with PIO and Joystick interface.

I never found in RomWBW before

- using of IM2
- loading of the I-Register
- an interrupt table where I can place ISR-adresses for my periphery

IÂŽm not shure that RomWBW is designed for this and we have no problems
with memeory mapping.

What do You think about using of an Z80-DART or Z80-SIO for serial
communication on ZETA -SBC and communication in IM2 to replace the
16550? On ECB-ModPrn this is running. Only the driver is not finished yet...

Best regards


Wolfgang

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC.
While the redesign is mostly to allow it to run FUZIX, it generally
increases the system flexibility and the new features might be useful
for other OSes as well. The design has been prototyped and it is
working properly. I'll be ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also
as vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages
in 1 MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and
less power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is
unchanged so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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Dr.-Ing. Wolfgang Kabatzke
Hansastrasse 9

DE - 21 502 Geesthacht
Deutschland / Germany

Phone: [phone] NEW!!!

[Wayne Warthen]

Hi Wolfgang,

You are entirely correct that RomWBW is lacking any support for interrupt
processing. I don't see much point in implementing mode 1 interrupt
processing. Mode 2 makes sense. It could already be implemented for N8
and Mark IV, but I have never gotten around to it. With Zeta implementing
CTC, I will probably try to get a minimal framework for interrupt handling
in place (at least a timer interrupt). As you point out, need to be
careful of the bank switching.

--Wayne

On Thursday, February 12, 2015 at 3:54:06 PM UTC-8, Dr. Wolfgang Kabatzke

Post by Wolfgang Kabatzke
Hi,
looks great! I read with big interest that You now use an CTC for clock
generating on the SBC. This is simialar to my ECB-ModPrn. Which OS is
running and use You RomWBW? If there is more time I plan to install an
interrupt driven driver for ECB-ModPrn and the development of an low cost
version of Centronics with PIO and Joystick interface.
I never found in RomWBW before
- using of IM2
- loading of the I-Register
- an interrupt table where I can place ISR-adresses for my periphery
IÂŽm not shure that RomWBW is designed for this and we have no problems
with memeory mapping.
What do You think about using of an Z80-DART or Z80-SIO for serial
communication on ZETA -SBC and communication in IM2 to replace the 16550?
On ECB-ModPrn this is running. Only the driver is not finished yet...
Best regards
Wolfgang
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
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Dr.-Ing. Wolfgang Kabatzke
Hansastrasse 9
DE - 21 502 Geesthacht
Deutschland / Germany
Phone: [phone] NEW!!!

[Max Scane]

The benefit of Mode 2 interrupts is that you can move the vector table
(reference by the I register) into high memory and it won't be impacted by
bank switches, that is assuming you are using a common bank in high memory.

Otherwise having a periodic interrupt and bank switching bets messy as you
have to disable interrupts during the switch and ensure the vector is in
place in the new bank.

Max

Post by Wayne Warthen
Hi Wolfgang,
You are entirely correct that RomWBW is lacking any support for interrupt
processing. I don't see much point in implementing mode 1 interrupt
processing. Mode 2 makes sense. It could already be implemented for N8
and Mark IV, but I have never gotten around to it. With Zeta implementing
CTC, I will probably try to get a minimal framework for interrupt handling
in place (at least a timer interrupt). As you point out, need to be
careful of the bank switching.
--Wayne
On Thursday, February 12, 2015 at 3:54:06 PM UTC-8, Dr. Wolfgang Kabatzke

Post by Wolfgang Kabatzke
Hi,
looks great! I read with big interest that You now use an CTC for clock
generating on the SBC. This is simialar to my ECB-ModPrn. Which OS is
running and use You RomWBW? If there is more time I plan to install an
interrupt driven driver for ECB-ModPrn and the development of an low cost
version of Centronics with PIO and Joystick interface.
I never found in RomWBW before
- using of IM2
- loading of the I-Register
- an interrupt table where I can place ISR-adresses for my periphery
IÂŽm not shure that RomWBW is designed for this and we have no problems
with memeory mapping.
What do You think about using of an Z80-DART or Z80-SIO for serial
communication on ZETA -SBC and communication in IM2 to replace the 16550?
On ECB-ModPrn this is running. Only the driver is not finished yet...
Best regards
Wolfgang
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
More information about this project: http://www.malinov.com/Home/
sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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Dr.-Ing. Wolfgang Kabatzke
Hansastrasse 9
DE - 21 502 Geesthacht
Deutschland / Germany
Phone: [phone] NEW!!!
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[Sergey]

Hi Wolfgang,

I added support for the board to RomWBW, so that I can boot CP/M and ZSDOS
on the new board. Modifications include memory mapping and FDC. It doesn't
use CTC or interrupts mode 2 yet. I wrote a simple program to test the CTC
and interrupts and it works fine.

I exchanged a couple of emails with Wayne about interrupt support in
RomWBW. I think it should be possible - it will need to setup the "I"
register to point to the upper memory bank, and place the interrupt table
and ISRs (or ISR proxies) there.

Thanks,
Sergey

On Thursday, February 12, 2015 at 3:54:06 PM UTC-8, Dr. Wolfgang Kabatzke

Post by Wolfgang Kabatzke
Hi,
looks great! I read with big interest that You now use an CTC for clock
generating on the SBC. This is simialar to my ECB-ModPrn. Which OS is
running and use You RomWBW? If there is more time I plan to install an
interrupt driven driver for ECB-ModPrn and the development of an low cost
version of Centronics with PIO and Joystick interface.
I never found in RomWBW before
- using of IM2
- loading of the I-Register
- an interrupt table where I can place ISR-adresses for my periphery
IÂŽm not shure that RomWBW is designed for this and we have no problems
with memeory mapping.
What do You think about using of an Z80-DART or Z80-SIO for serial
communication on ZETA -SBC and communication in IM2 to replace the 16550?
On ECB-ModPrn this is running. Only the driver is not finished yet...
Best regards
Wolfgang
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
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Dr.-Ing. Wolfgang Kabatzke
Hansastrasse 9
DE - 21 502 Geesthacht
Deutschland / Germany
Phone: [phone] NEW!!!

[Wolfgang Kabatzke]

Hi Sergey,

this is absolute interesting! These points I looked for, but my problem
is at the moment the time and I missed some examples to implement
modifications (for example own drivers etc.) to modify RomWBW and some
tips or some "doÂŽs and donÂŽts".

May You give me please the information with files You modified? The
programming of Interrupt Mode 2 with CTC, SIO and PIO is not my problem.
I have experiences in this.

ThankÂŽs for help

Best regards

Wolfgang

Post by Wayne Warthen
Hi Wolfgang,
I added support for the board to RomWBW, so that I can boot CP/M and
ZSDOS on the new board. Modifications include memory mapping and FDC.
It doesn't use CTC or interrupts mode 2 yet. I wrote a simple program
to test the CTC and interrupts and it works fine.
I exchanged a couple of emails with Wayne about interrupt support in
RomWBW. I think it should be possible - it will need to setup the "I"
register to point to the upper memory bank, and place the interrupt
table and ISRs (or ISR proxies) there.
Thanks,
Sergey
On Thursday, February 12, 2015 at 3:54:06 PM UTC-8, Dr. Wolfgang
Hi,
looks great! I read with big interest that You now use an CTC for
clock generating on the SBC. This is simialar to my ECB-ModPrn.
Which OS is running and use You RomWBW? If there is more time I
plan to install an interrupt driven driver for ECB-ModPrn and the
development of an low cost version of Centronics with PIO and
Joystick interface.
I never found in RomWBW before
- using of IM2
- loading of the I-Register
- an interrupt table where I can place ISR-adresses for my periphery
IÂŽm not shure that RomWBW is designed for this and we have no
problems with memeory mapping.
What do You think about using of an Z80-DART or Z80-SIO for serial
communication on ZETA -SBC and communication in IM2 to replace the
16550? On ECB-ModPrn this is running. Only the driver is not finished yet...
Best regards
Wolfgang

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC.
While the redesign is mostly to allow it to run FUZIX, it
generally increases the system flexibility and the new features
might be useful for other OSes as well. The design has been
prototyped and it is working properly. I'll be ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link
below). Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and
also as vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16
KiB memory banks, each one of them be mapped to any one of 64 16
KiB pages in 1 MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is
more integrated, and saves 5 logic ICs. Also it is also easier to
find, and less power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1).
The location of external connectors and the parallel port header
is unchanged so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
<http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2>
Special thanks go to Alan Cox and Wayne Warthen for their design
ideas and help with troubleshooting.
Thanks,
Sergey
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--
Dr.-Ing. Wolfgang Kabatzke
Hansastrasse 9
DE - 21 502 Geesthacht
Deutschland / Germany
Phone: [phone] NEW!!!
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Hansastrasse 9

DE - 21 502 Geesthacht
Deutschland / Germany

Phone: [phone] NEW!!!

[Don Caprio]

I'll take one please.

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC.
While the redesign is mostly to allow it to run FUZIX, it generally
increases the system flexibility and the new features might be useful
for other OSes as well. The design has been prototyped and it is
working properly. I'll be ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also
as vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages
in 1 MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and
less power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is
unchanged so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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Don Caprio
***@gmail.com

[Max Scane]

Hi Sergey,

The updated design looks great. Please count me in for one!

I'm wondering how important is it to have a floppy controller on board?
Would you consider trading the floppy for an 8 bit bus connected IDE port
(like the Mark IV). It could be used for a compact flash or industrial
flash drive in 8 bit mode.

The CTC is a good addition to provide vectored interrupts as well as a
interval timer. Is there a spare channel to take an interrupt form the
8255? I think the PPP puts the 8255 in mode 2 so any keyboard activity
could generate an interrupt instead of being polled.

Would there be any room for a Z80-DMA chip with the above scenario? If you
are looking to run FUZIX it might be useful.


Cheers!

Max

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
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[Sergey]

Hi Max,

I really like having the floppy support but maybe that is just my nostalgia
thing :-)

I don't see much point of having on-board IDE: If needed IDE drive can be
connected using a PPIDE board, also an SD card can be used through a
ParPortProp board.

I like the idea of connecting 8255's PC3 (INTR in mode 2) to the CTC to
generate the interrupt when data is written to 8255 by ParPortProp.
Unfortunately all CTC trigger inputs are used, but I can put a jumper to
choose between FDC and 8255. Or maybe just wire it to the 8255 permanently
- interrupt driven I/O doesn't that useful for FDC anyway.

No space for DMAC - sorry :-) [unless I get rid of some another 40-pin IC]

Thanks,
Sergey

Post by Max Scane
Hi Sergey,
The updated design looks great. Please count me in for one!
I'm wondering how important is it to have a floppy controller on board?
Would you consider trading the floppy for an 8 bit bus connected IDE port
(like the Mark IV). It could be used for a compact flash or industrial
flash drive in 8 bit mode.
The CTC is a good addition to provide vectored interrupts as well as a
interval timer. Is there a spare channel to take an interrupt form the
8255? I think the PPP puts the 8255 in mode 2 so any keyboard activity
could generate an interrupt instead of being polled.
Would there be any room for a Z80-DMA chip with the above scenario? If you
are looking to run FUZIX it might be useful.
Cheers!
Max

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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[Max Scane]

The benefit of directly connecting the IDE to the bus is more around
speed. Bit banging the 8255 is relatively slow. With the PPP installed
you can't have a CF drive as well. I look on the SD card as more of a
floppy replacement.

Perhaps replace the 16C550 with a DART or 85C30 to free up a CTC channel
for the 8255 interrupt. It would need to be jumper settable as in PPIDE
mode it is used otherwise.


Now if you are really into radical surgery, how about replacing the Z80
with a Z180, adding an on-board SD card at the front (like the PPP) putting
two serial ports on the back, moving the PPI connector towards the back and
using it to accept a half size daughter card (like the original PPP) with
maybe stackable connectors for additional boards?

but then it wouldn't be a Zeta anymore I guess.


Cheers!

Max

Post by Sergey
Hi Max,
I really like having the floppy support but maybe that is just my
nostalgia thing :-)
I don't see much point of having on-board IDE: If needed IDE drive can be
connected using a PPIDE board, also an SD card can be used through a
ParPortProp board.
I like the idea of connecting 8255's PC3 (INTR in mode 2) to the CTC to
generate the interrupt when data is written to 8255 by ParPortProp.
Unfortunately all CTC trigger inputs are used, but I can put a jumper to
choose between FDC and 8255. Or maybe just wire it to the 8255 permanently
- interrupt driven I/O doesn't that useful for FDC anyway.
No space for DMAC - sorry :-) [unless I get rid of some another 40-pin IC]
Thanks,
Sergey

Post by Max Scane
Hi Sergey,
The updated design looks great. Please count me in for one!
I'm wondering how important is it to have a floppy controller on board?
Would you consider trading the floppy for an 8 bit bus connected IDE port
(like the Mark IV). It could be used for a compact flash or industrial
flash drive in 8 bit mode.
The CTC is a good addition to provide vectored interrupts as well as a
interval timer. Is there a spare channel to take an interrupt form the
8255? I think the PPP puts the 8255 in mode 2 so any keyboard activity
could generate an interrupt instead of being polled.
Would there be any room for a Z80-DMA chip with the above scenario? If
you are looking to run FUZIX it might be useful.
Cheers!
Max

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
More information about this project: http://www.malinov.com/Home/
sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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[Sergey]

Max,

In this case it looks like using Z180 (Z8S180) would be a better solution.
Perhaps add a dual 16552 UART (I really hate that in Z180 UART clock
depends on CPU clock). Agree that won't be Zeta anymore :-) But I am sure
we can find some another name.

Thanks,
Sergey

Post by Max Scane
The benefit of directly connecting the IDE to the bus is more around
speed. Bit banging the 8255 is relatively slow. With the PPP installed
you can't have a CF drive as well. I look on the SD card as more of a
floppy replacement.
Perhaps replace the 16C550 with a DART or 85C30 to free up a CTC channel
for the 8255 interrupt. It would need to be jumper settable as in PPIDE
mode it is used otherwise.
Now if you are really into radical surgery, how about replacing the Z80
with a Z180, adding an on-board SD card at the front (like the PPP) putting
two serial ports on the back, moving the PPI connector towards the back and
using it to accept a half size daughter card (like the original PPP) with
maybe stackable connectors for additional boards?
but then it wouldn't be a Zeta anymore I guess.
Cheers!
Max

Post by Sergey
Hi Max,
I really like having the floppy support but maybe that is just my
nostalgia thing :-)
I don't see much point of having on-board IDE: If needed IDE drive can be
connected using a PPIDE board, also an SD card can be used through a
ParPortProp board.
I like the idea of connecting 8255's PC3 (INTR in mode 2) to the CTC to
generate the interrupt when data is written to 8255 by ParPortProp.
Unfortunately all CTC trigger inputs are used, but I can put a jumper to
choose between FDC and 8255. Or maybe just wire it to the 8255 permanently
- interrupt driven I/O doesn't that useful for FDC anyway.
No space for DMAC - sorry :-) [unless I get rid of some another 40-pin IC]
Thanks,
Sergey

Post by Max Scane
Hi Sergey,
The updated design looks great. Please count me in for one!
I'm wondering how important is it to have a floppy controller on board?
Would you consider trading the floppy for an 8 bit bus connected IDE port
(like the Mark IV). It could be used for a compact flash or industrial
flash drive in 8 bit mode.
The CTC is a good addition to provide vectored interrupts as well as a
interval timer. Is there a spare channel to take an interrupt form the
8255? I think the PPP puts the 8255 in mode 2 so any keyboard activity
could generate an interrupt instead of being polled.
Would there be any room for a Z80-DMA chip with the above scenario? If
you are looking to run FUZIX it might be useful.
Cheers!
Max

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also
as vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
More information about this project: http://www.malinov.com/Home/
sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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[Max Scane]

I really like having two types of disk media. I use the SD card to
directly import files from a FAT file system and have a CF or industrial
flash module as my main disk.

I also like having two serial ports so I can use one for a serial console
and one for file transfers.

The Z180 has the benefit of internal peripherals such as timer, DMA,
vectored interrupts and MMU. But yes the serial ports are a bit of a pain.

As a standalone board the N8 is a really nice board. If it had an 80x25
video and a better keyboard controller it would be almost perfect. The Mark
IV is also up there for bus connected systems.

The Zeta form factor is great especially for new builders as it an all in
one board.

Another thought comes to mind and that is to perhaps make room for a USB
interface instead of a serial port?

Maybe something like the FTDI USB-> DE9 module:

http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_DB9-USB.pdf

Lost of brainstorming here...

Cheers!

Post by Sergey
Max,
In this case it looks like using Z180 (Z8S180) would be a better solution.
Perhaps add a dual 16552 UART (I really hate that in Z180 UART clock
depends on CPU clock). Agree that won't be Zeta anymore :-) But I am sure
we can find some another name.
Thanks,
Sergey

Post by Max Scane
The benefit of directly connecting the IDE to the bus is more around
speed. Bit banging the 8255 is relatively slow. With the PPP installed
you can't have a CF drive as well. I look on the SD card as more of a
floppy replacement.
Perhaps replace the 16C550 with a DART or 85C30 to free up a CTC channel
for the 8255 interrupt. It would need to be jumper settable as in PPIDE
mode it is used otherwise.
Now if you are really into radical surgery, how about replacing the Z80
with a Z180, adding an on-board SD card at the front (like the PPP) putting
two serial ports on the back, moving the PPI connector towards the back and
using it to accept a half size daughter card (like the original PPP) with
maybe stackable connectors for additional boards?
but then it wouldn't be a Zeta anymore I guess.
Cheers!
Max

Post by Sergey
Hi Max,
I really like having the floppy support but maybe that is just my
nostalgia thing :-)
I don't see much point of having on-board IDE: If needed IDE drive can
be connected using a PPIDE board, also an SD card can be used through a
ParPortProp board.
I like the idea of connecting 8255's PC3 (INTR in mode 2) to the CTC to
generate the interrupt when data is written to 8255 by ParPortProp.
Unfortunately all CTC trigger inputs are used, but I can put a jumper to
choose between FDC and 8255. Or maybe just wire it to the 8255 permanently
- interrupt driven I/O doesn't that useful for FDC anyway.
No space for DMAC - sorry :-) [unless I get rid of some another 40-pin IC]
Thanks,
Sergey

Post by Max Scane
Hi Sergey,
The updated design looks great. Please count me in for one!
I'm wondering how important is it to have a floppy controller on
board? Would you consider trading the floppy for an 8 bit bus connected
IDE port (like the Mark IV). It could be used for a compact flash or
industrial flash drive in 8 bit mode.
The CTC is a good addition to provide vectored interrupts as well as a
interval timer. Is there a spare channel to take an interrupt form the
8255? I think the PPP puts the 8255 in mode 2 so any keyboard activity
could generate an interrupt instead of being polled.
Would there be any room for a Z80-DMA chip with the above scenario? If
you are looking to run FUZIX it might be useful.
Cheers!
Max

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC.
While the redesign is mostly to allow it to run FUZIX, it generally
increases the system flexibility and the new features might be useful for
other OSes as well. The design has been prototyped and it is working
properly. I'll be ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also
as vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
More information about this project: http://www.malinov.com/Home/se
rgeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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[Anthony DeStefano]

Post by Max Scane
Hi Sergey,
The updated design looks great. Please count me in for one!
I'm wondering how important is it to have a floppy controller on
board? Would you consider trading the floppy for an 8 bit bus
connected IDE port (like the Mark IV). It could be used for a compact
flash or industrial flash drive in 8 bit mode.
The CTC is a good addition to provide vectored interrupts as well as a
interval timer. Is there a spare channel to take an interrupt form the
8255? I think the PPP puts the 8255 in mode 2 so any keyboard activity
could generate an interrupt instead of being polled.

I'd second the tying the keyboard into an interrupt. When I wrote the
N8VEM PropIO code for FUZIX I was surprised there was no interrupt
routed on the board. One of these days I do need to fix that up and get
it tied into the console subsystem.

--
Anthony DeStefano ***@fastmail.fm

[Borut]

Thanks Sergey, count me for one.

Bo/

[John Coffman]

Max, Sergey,

The 8-bit IDE bus on the Mark IV was an experiment that has proved to be
highly successful. It is a very fast IDE port, and I have found no CF
cards that do not work at full speed.

You might wish to consider using the PLCC44 version of the 37C65 -- it
saves a lot of board space vs. the DIP40. The PLCC44 is used on the
SBC-188.

A version of FUZIX is in the works for the Mark IV and P112 boards.
Will S. is working on this project.

--John

BTW: count me in for this updated Zeta.

Post by Max Scane
Hi Sergey,
The updated design looks great. Please count me in for one!
I'm wondering how important is it to have a floppy controller on
board? Would you consider trading the floppy for an 8 bit bus
connected IDE port (like the Mark IV). It could be used for a compact
flash or industrial flash drive in 8 bit mode.
The CTC is a good addition to provide vectored interrupts as well as a
interval timer. Is there a spare channel to take an interrupt form
the 8255? I think the  PPP puts the 8255 in mode 2 so any keyboard
activity could generate an interrupt instead of being polled.
Would there be any room for a Z80-DMA chip with the above scenario? If
you are looking to run FUZIX it might be useful.
Cheers!
Max
Hi,
For the last few weeks I've been working on redesign of Zeta SBC.
While the redesign is mostly to allow it to run FUZIX, it
generally increases the system flexibility and the new features
might be useful for other OSes as well. The design has been
prototyped and it is working properly. I'll be ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link
below). Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and
also as vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16
KiB memory banks, each one of them be mapped to any one of 64 16
KiB pages in 1 MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is
more integrated, and saves 5 logic ICs. Also it is also easier to
find, and less power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1).
The location of external connectors and the parallel port header
is unchanged so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design
ideas and help with troubleshooting.
Thanks,
Sergey
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[Andrew Bingham]

I had really good luck with the PLCC44 37C65 on my SBC-188.

Post by John Coffman
Max, Sergey,
The 8-bit IDE bus on the Mark IV was an experiment that has proved to be
highly successful. It is a very fast IDE port, and I have found no CF
cards that do not work at full speed.
You might wish to consider using the PLCC44 version of the 37C65 -- it
saves a lot of board space vs. the DIP40. The PLCC44 is used on the
SBC-188.
A version of FUZIX is in the works for the Mark IV and P112 boards. Will
S. is working on this project.
--John
BTW: count me in for this updated Zeta.
Hi Sergey,
The updated design looks great. Please count me in for one!
I'm wondering how important is it to have a floppy controller on
board? Would you consider trading the floppy for an 8 bit bus connected
IDE port (like the Mark IV). It could be used for a compact flash or
industrial flash drive in 8 bit mode.
The CTC is a good addition to provide vectored interrupts as well as a
interval timer. Is there a spare channel to take an interrupt form the
8255? I think the  PPP puts the 8255 in mode 2 so any keyboard activity
could generate an interrupt instead of being polled.
Would there be any room for a Z80-DMA chip with the above scenario? If
you are looking to run FUZIX it might be useful.
Cheers!
Max

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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[Tom Lafleur]

I'll take one...

thanks

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
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--
~~ _/) ~~~~ _/) ~~~~ _/) ~~~~ _/) ~~

Tom Lafleur

[AG5AT]

I am good for one
Aug

[Fabio Battaglia]

I'll take 3x pcb for this board!
Thanks,
Fabio

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
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[Borut]

Hi Sergey!

Does using CTC limit maximum CPU speed?
What i like about Zeta is that it easily runs at 20Mhz.

Best regards,
Bo/

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey

[Sergey]

Borut,

I had the same concern. It looks that the fastest CTC available is rated
for 10 MHz. I have one, and I tried it at 20 MHz. It worked fine, at least
for a short test. Possibly it needs more thorough testing, including in
timer mode (which counts the CPU clock pulses).

Thanks,
Sergey

Post by Borut
Hi Sergey!
Does using CTC limit maximum CPU speed?
What i like about Zeta is that it easily runs at 20Mhz.
Best regards,
Bo/

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey

[Martin Lukasek]

Hi Sergey,

great, I will look at it during weekend. Count me in for a board, please.

Best regards

Martin

From: ***@googlegroups.com [mailto:***@googlegroups.com] On Behalf Of Sergey
Sent: Friday, February 13, 2015 12:05 AM
To: ***@googlegroups.com
Subject: [N8VEM: 19281] Zeta SBC V2

Hi,

For the last few weeks I've been working on redesign of Zeta SBC. While the redesign is mostly to allow it to run FUZIX, it generally increases the system flexibility and the new features might be useful for other OSes as well. The design has been prototyped and it is working properly. I'll be ordering PCBs soon.

How you can help?
- Please review schematic, PCB design, documentation (see link below). Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).

What's new:
- Added Z80 CTC. It is used to generate periodic interrupts, and also as vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1 MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more integrated, and saves 5 logic ICs. Also it is also easier to find, and less power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.

The new design still has the same form factor as Zeta SBC (V1). The location of external connectors and the parallel port header is unchanged so it still can be stacked with ParPortProp.

More information about this project: http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2

Special thanks go to Alan Cox and Wayne Warthen for their design ideas and help with troubleshooting.

Thanks,
Sergey
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[Elsid]

One for me please.

Leon Byles

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey

[Dylan Distasio]

I will take one, please.

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
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[Gary Kaufman]

Sergey -

Two for me please!

- Gary

[Anthony DeStefano]

Add another name to the list of those that would be interested. I'd also
be interested in a ParPortProp board to go with it if someone is
thinking about making another run of them, too.

--
Anthony DeStefano ***@fastmail.fm

[Brian Marstella]

Hi, Sergey,

Looks great, please count me in for one.

Thanks! Brian

[Ian May]

Hi Sergey,
I'd like to make a suggestion regarding the 34 pin FDC header. I bought
some nice boxed and keyed right angle headers for my Zeta. One type even
has side ejectors and it still fits along side the DC power connector.
Unfortunately if I want to use the keying the cable has to be fitted from
the "inside" of the board rather than from the outside edge of the board.
I'm not sure if there are two right angle versions available (i.e. 90
degrees and 270 degrees) or if the only type made is the one that I have.
Does anyone else know? Anyway could you consider re-arranging the pin out
to suit a right angle boxed header?
Cheers,
Ian.

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
--
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[Sergey]

Hi Ian,

The floppy connector on Zeta is oriented the same way as the floppy
interface connector on a standard 3.5" floppy drive. This allows using a
very short flat cable to connect Zeta to the floppy drive (presumably
assembled on the top of that Zeta) without twisting the cable. If you like
to use right angle connector, you can consider building a special cable,
with a flipped connector on the Zeta's end. Or you can simply remove the
orientation notch on the IDC connector (there are some floppy cables
without this notch). The floppy interface uses open-collector outputs and
it is fairly resilient to cable connected the wrong way (an indicator of
incorrect orientation is floppy activity LED coming on when power is
applied to the board).

Thanks,
Sergey

Post by Max Scane
Hi Sergey,
I'd like to make a suggestion regarding the 34 pin FDC header. I bought
some nice boxed and keyed right angle headers for my Zeta. One type even
has side ejectors and it still fits along side the DC power connector.
Unfortunately if I want to use the keying the cable has to be fitted from
the "inside" of the board rather than from the outside edge of the board.
I'm not sure if there are two right angle versions available (i.e. 90
degrees and 270 degrees) or if the only type made is the one that I have.
Does anyone else know? Anyway could you consider re-arranging the pin out
to suit a right angle boxed header?
Cheers,
Ian.

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey
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.
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[Sergey]

A schematic update:
The CTC's CH3 trigger input is now connected to 8255 PPI port PC3, instead
of the FDC INT signal.
In modes 1 and 2 (ParPortProp is using mode 2), 8255 can use port PC3 to
generate interrupts when data is received from the device, or when output
buffer is empty. This will allow interrupt driven I/O for ParPortProp. That
could be especially useful in multitasking environments. (To make it work
some changes are required in ParPortProp communication protocol)

Interrupts are not really useful with FDC without a DMAC anyway.

Thanks,
Sergey

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey

[roman fulek]

Just curious. Sergey why have you not used PC8477BV-1 ?

And I agree with everything what you said about floppy and Zeta. It is
nostalgia pure :-) I would never had built Zeta, did it not have floppy
controller. You can count me in for one PCB.

Roman

Post by Sergey
The CTC's CH3 trigger input is now connected to 8255 PPI port PC3, instead
of the FDC INT signal.
In modes 1 and 2 (ParPortProp is using mode 2), 8255 can use port PC3 to
generate interrupts when data is received from the device, or when output
buffer is empty. This will allow interrupt driven I/O for ParPortProp. That
could be especially useful in multitasking environments. (To make it work
some changes are required in ParPortProp communication protocol)
Interrupts are not really useful with FDC without a DMAC anyway.
Thanks,
Sergey

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey

[Sergey]

Roman,

PC8477 is somewhat more difficult to get than 37C65. PC8477 has some
advantages when used in PC-like system (it implements address decode for
registers for example), but not so much in a system where strict PC
compatibility is not required. 68-pin PLCC takes a bit more PCB space. In
general PLCC chips are a bit more difficult to work with, and also PCB
routing becomes more complicated. Finally I like the more vintage look of
DIP packages, and I happen to have a few 37C65's :-)

Thanks,
Sergey

Post by roman fulek
Just curious. Sergey why have you not used PC8477BV-1 ?
And I agree with everything what you said about floppy and Zeta. It is
nostalgia pure :-) I would never had built Zeta, did it not have floppy
controller. You can count me in for one PCB.
Roman

Post by Sergey
The CTC's CH3 trigger input is now connected to 8255 PPI port PC3,
instead of the FDC INT signal.
In modes 1 and 2 (ParPortProp is using mode 2), 8255 can use port PC3 to
generate interrupts when data is received from the device, or when output
buffer is empty. This will allow interrupt driven I/O for ParPortProp. That
could be especially useful in multitasking environments. (To make it work
some changes are required in ParPortProp communication protocol)
Interrupts are not really useful with FDC without a DMAC anyway.
Thanks,
Sergey

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey

[Alex Swedenburg]

Count me in for a board, too.

[Sergey]

Update: I placed the PCB order earlier today. I expect to get boards by
mid-March. Now it looks that I'll be pretty busy during that time (spring
break). Hopefully I'll be ready to send boards by the end of this month.

Thanks,
Sergey

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey

[J. Alexander Jacocks]

Sergey,

Thanks much for your fantastic work on this project. I have gotten a lot
of enjoyment out of my Zeta.

- Alex

Post by Sergey
Update: I placed the PCB order earlier today. I expect to get boards by
mid-March. Now it looks that I'll be pretty busy during that time (spring
break). Hopefully I'll be ready to send boards by the end of this month.
Thanks,
Sergey

Post by Sergey
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While
the redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
More information about this project: http://www.malinov.com/Home/
sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas
and help with troubleshooting.
Thanks,
Sergey

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