Sergey
2015-02-12 23:05:23 UTC
Hi,
For the last few weeks I've been working on redesign of Zeta SBC. While the
redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
What's new:
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
More information about this project:
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
For the last few weeks I've been working on redesign of Zeta SBC. While the
redesign is mostly to allow it to run FUZIX, it generally increases the
system flexibility and the new features might be useful for other OSes as
well. The design has been prototyped and it is working properly. I'll be
ordering PCBs soon.
How you can help?
- Please review schematic, PCB design, documentation (see link below).
Provide me a feedback.
- Let me know if you want to get a PCB (and how many?).
What's new:
- Added Z80 CTC. It is used to generate periodic interrupts, and also as
vectored interrupt controller for UART and FDC
- Redesigned memory banking mechanism. The new design has four 16 KiB
memory banks, each one of them be mapped to any one of 64 16 KiB pages in 1
MiB system memory.
- FDC9266 replaced with the PDIP version of 37C65. This FDC is more
integrated, and saves 5 logic ICs. Also it is also easier to find, and less
power hungry.
- CTS/RTS is used for hardware handshaking instead of DTR/DSR.
The new design still has the same form factor as Zeta SBC (V1). The
location of external connectors and the parallel port header is unchanged
so it still can be stacked with ParPortProp.
More information about this project:
http://www.malinov.com/Home/sergeys-projects/zeta-sbc-v2
Special thanks go to Alan Cox and Wayne Warthen for their design ideas and
help with troubleshooting.
Thanks,
Sergey
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