[N8VEM: 17552] RE: 6x0x prototype board possile ECB Timing issue

[Andrew Lynch]

Hi



Unless I missed something I don't think this issue was ever properly vetted.




Does anyone have an answer or understand what is happening with the 6x0x ECB
interface?

There may be a problem with the logic or a timing issue. The ECB interface
has always been the trickiest part.



Thanks and have a nice day!

Andrew Lynch



From: Dan Werner [mailto:danwerner21-***@public.gmane.org]
Sent: Saturday, March 1, 2014 3:38 PM
To: 'John Coffman'; 'Andrew Lynch'
Cc: 'Borut Korosin'; 'Kip Koon'
Subject: 6x0x prototype board possile ECB Timing issue



HELP!!



I am working on getting the ECB Disk IO V3 board to work with the 6x0x
board. I had no problems getting the PPPIDE working, but have had no luck
with the floppy FDC9266.



Please note that I am a software guy, so let me know if I am way off on what
I am seeing here.



Take a look at the attached timing diagram. I attached my logic analyzer
to the Disk IO board in the following way:



A0-A7 are attached to D0-D7 on the 9266

A8=RD on the 9266 (PIN 2)

A9=WR on the 9266 (PIN 3)

AA=A0 on the 9266 (PIN 5)

AB = FDC_CS on U8 (PIN 10)

AC = IDE_FDC on U8 (PIN 15)



I have a simple 6502 program running to read and then write to the 9266



LOOP:

LDA $E030

STA $E030

LDA $E031

STA $E031

JMP LOOP



Looks to me like CS is going low before the RD or WR pins are going low, so
it I am not getting good reads or writes on the 9266. Does this look
correct?



If so, do we need to make a change to the ECB interface on the 6x0x?



Thanks!



Dan Werner

[Dan Werner]

I sent a timing diagram out, and John confirmed that it looked correct to
him. However I still do not have the Disk IO V3 floppy controller talking
to the 6x0x board. I am continuing to troubleshoot -- in the end I am
sure it will be something stupid simple J



Dan





From: Andrew Lynch [mailto:LYNCHAJ-***@public.gmane.org]
Sent: Monday, March 10, 2014 7:07 PM
To: 'Dan Werner'; 'John Coffman'; 'Borut Korosin'; 'Kip Koon'
Cc: n8vem-/***@public.gmane.org
Subject: RE: 6x0x prototype board possile ECB Timing issue



Hi



Unless I missed something I don't think this issue was ever properly vetted.




Does anyone have an answer or understand what is happening with the 6x0x ECB
interface?

There may be a problem with the logic or a timing issue. The ECB interface
has always been the trickiest part.



Thanks and have a nice day!

Andrew Lynch



From: Dan Werner [mailto:danwerner21-***@public.gmane.org]
Sent: Saturday, March 1, 2014 3:38 PM
To: 'John Coffman'; 'Andrew Lynch'
Cc: 'Borut Korosin'; 'Kip Koon'
Subject: 6x0x prototype board possile ECB Timing issue



HELP!!



I am working on getting the ECB Disk IO V3 board to work with the 6x0x
board. I had no problems getting the PPPIDE working, but have had no luck
with the floppy FDC9266.



Please note that I am a software guy, so let me know if I am way off on what
I am seeing here.



Take a look at the attached timing diagram. I attached my logic analyzer
to the Disk IO board in the following way:



A0-A7 are attached to D0-D7 on the 9266

A8=RD on the 9266 (PIN 2)

A9=WR on the 9266 (PIN 3)

AA=A0 on the 9266 (PIN 5)

AB = FDC_CS on U8 (PIN 10)

AC = IDE_FDC on U8 (PIN 15)



I have a simple 6502 program running to read and then write to the 9266



LOOP:

LDA $E030

STA $E030

LDA $E031

STA $E031

JMP LOOP



Looks to me like CS is going low before the RD or WR pins are going low, so
it I am not getting good reads or writes on the 9266. Does this look
correct?



If so, do we need to make a change to the ECB interface on the 6x0x?



Thanks!



Dan Werner

[Borut Korosin]

Dan,

Could you please make another timing diagram, this time including E, Q and
R/W at the processor if you have 6809.
If you are using 6502, please include PHI0, PHI1, PHI2 and R/W.
I think we have to compare timings at the peripheral with the processors.


lp, Bo/

Post by Dan Werner
I sent a timing diagram out, and John confirmed that it looked correct to
him. However I still do not have the Disk IO V3 floppy controller talking
to the 6x0x board. I am continuing to troubleshoot -- in the end I am
sure it will be something stupid simple J
Dan
*Sent:* Monday, March 10, 2014 7:07 PM
*To:* 'Dan Werner'; 'John Coffman'; 'Borut Korosin'; 'Kip Koon'
*Subject:* RE: 6x0x prototype board possile ECB Timing issue
Hi
Unless I missed something I don't think this issue was ever properly vetted.
Does anyone have an answer or understand what is happening with the 6x0x
ECB interface?
There may be a problem with the logic or a timing issue. The ECB
interface has always been the trickiest part.
Thanks and have a nice day!
Andrew Lynch
*Sent:* Saturday, March 1, 2014 3:38 PM
*To:* 'John Coffman'; 'Andrew Lynch'
*Cc:* 'Borut Korosin'; 'Kip Koon'
*Subject:* 6x0x prototype board possile ECB Timing issue
HELP!!
I am working on getting the ECB Disk IO V3 board to work with the 6x0x
board. I had no problems getting the PPPIDE working, but have had no luck
with the floppy FDC9266.
Please note that I am a software guy, so let me know if I am way off on
what I am seeing here.
Take a look at the attached timing diagram. I attached my logic analyzer
A0-A7 are attached to D0-D7 on the 9266
A8=RD on the 9266 (PIN 2)
A9=WR on the 9266 (PIN 3)
AA=A0 on the 9266 (PIN 5)
AB = FDC_CS on U8 (PIN 10)
AC = IDE_FDC on U8 (PIN 15)
I have a simple 6502 program running to read and then write to the 9266
LDA $E030
STA $E030
LDA $E031
STA $E031
JMP LOOP
Looks to me like CS is going low before the RD or WR pins are going low,
so it I am not getting good reads or writes on the 9266. Does this look
correct?
If so, do we need to make a change to the ECB interface on the 6x0x?
Thanks!
Dan Werner

[John Coffman]

Dan,

I was going to ask about /M1, but you have the chip selects correct, so
that signal must be okay. (High during /IORQ).

Have you been able to access any other peripheral on the ECB bus? There
is an 8255 on the DiskIO v3. Can you read & write the Control Register
of the 8255?

Other boards with registers you can write to and then read back: (off
the top of my head:)

MF/PIC -- register 7 of the Uart is a pure scratch register.
4MEM -- any of the mapping registers can be written and read back.
Color VDU -- parallel port

--John

Post by Borut Korosin
Dan,
Could you please make another timing diagram, this time including E, Q
and R/W at the processor if you have 6809.
If you are using 6502, please include PHI0, PHI1, PHI2 and R/W.
I think we have to compare timings at the peripheral with the processors.
lp, Bo/
I sent a timing diagram out, and John confirmed that it looked
correct to him. However I still do not have the Disk IO V3
floppy controller talking to the 6x0x board. I am continuing to
troubleshoot -- in the end I am sure it will be something stupid
simple J
Dan
*Sent:* Monday, March 10, 2014 7:07 PM
*To:* 'Dan Werner'; 'John Coffman'; 'Borut Korosin'; 'Kip Koon'
*Subject:* RE: 6x0x prototype board possile ECB Timing issue
Hi
Unless I missed something I don't think this issue was ever properly vetted.
Does anyone have an answer or understand what is happening with
the 6x0x ECB interface?
There may be a problem with the logic or a timing issue. The ECB
interface has always been the trickiest part.
Thanks and have a nice day!
Andrew Lynch
*Sent:* Saturday, March 1, 2014 3:38 PM
*To:* 'John Coffman'; 'Andrew Lynch'
*Cc:* 'Borut Korosin'; 'Kip Koon'
*Subject:* 6x0x prototype board possile ECB Timing issue
HELP!!
I am working on getting the ECB Disk IO V3 board to work with the
6x0x board. I had no problems getting the PPPIDE working, but
have had no luck with the floppy FDC9266.
Please note that I am a software guy, so let me know if I am way
off on what I am seeing here.
Take a look at the attached timing diagram. I attached my logic
A0-A7 are attached to D0-D7 on the 9266
A8=RD on the 9266 (PIN 2)
A9=WR on the 9266 (PIN 3)
AA=A0 on the 9266 (PIN 5)
AB = FDC_CS on U8 (PIN 10)
AC = IDE_FDC on U8 (PIN 15)
I have a simple 6502 program running to read and then write to the 9266
LDA $E030
STA $E030
LDA $E031
STA $E031
JMP LOOP
Looks to me like CS is going low before the RD or WR pins are
going low, so it I am not getting good reads or writes on the
9266. Does this look correct?
If so, do we need to make a change to the ECB interface on the 6x0x?
Thanks!
Dan Werner